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  • © 2012

Reliability, Availability and Serviceability of Networks-on-Chip

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  • Provides state-of-the-art research on the challenges to test, diagnose and tolerate faults in NoC-based systems

  • Includes numerous, current test strategies, including re-use of the network for core testing, test scheduling for the NoC reuse, test access methods and interface, efficient re-use of the network, and power-aware and thermal-aware NoC-based SoC testing

  • Offers a single source reference to the latest research, otherwise available only in disparate journals and conference proceedings

  • Includes supplementary material: sn.pub/extras

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USD 89.00
Price excludes VAT (USA)
  • ISBN: 978-1-4614-0791-1
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  • Readable on all devices
  • Own it forever
  • Exclusive offer for individuals only
  • Tax calculation will be finalised during checkout
Softcover Book
USD 119.99
Price excludes VAT (USA)
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USD 149.99
Price excludes VAT (USA)

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Table of contents (10 chapters)

  1. Front Matter

    Pages i-xiii
  2. Introduction

    • Érika Cota, Alexandre de Morais Amory, Marcelo Soares Lubaszewski
    Pages 1-9
  3. NoC Basics

    • Érika Cota, Alexandre de Morais Amory, Marcelo Soares Lubaszewski
    Pages 11-24
  4. Systems-on-Chip Testing

    • Érika Cota, Alexandre de Morais Amory, Marcelo Soares Lubaszewski
    Pages 25-58
  5. NoC Reuse for SoC Modular Testing

    • Érika Cota, Alexandre de Morais Amory, Marcelo Soares Lubaszewski
    Pages 59-83
  6. Advanced Approaches for NoC Reuse

    • Érika Cota, Alexandre de Morais Amory, Marcelo Soares Lubaszewski
    Pages 85-114
  7. Test and Diagnosis of Routers

    • Érika Cota, Alexandre de Morais Amory, Marcelo Soares Lubaszewski
    Pages 115-132
  8. Test and Diagnosis of Communication Channels

    • Érika Cota, Alexandre de Morais Amory, Marcelo Soares Lubaszewski
    Pages 133-154
  9. Error Control Coding and Retransmission

    • Érika Cota, Alexandre de Morais Amory, Marcelo Soares Lubaszewski
    Pages 155-173
  10. Error Location and Reconfiguration

    • Érika Cota, Alexandre de Morais Amory, Marcelo Soares Lubaszewski
    Pages 175-193
  11. Concluding Remarks

    • Érika Cota, Alexandre de Morais Amory, Marcelo Soares Lubaszewski
    Pages 195-200
  12. Back Matter

    Pages 201-209

About this book

This book presents an overview of the issues related to the test, diagnosis and fault-tolerance of Network on Chip-based systems.  It is the first book dedicated to the quality aspects of NoC-based systems and will serve as an invaluable reference to the problems, challenges, solutions, and trade-offs related to designing and implementing state-of-the-art, on-chip communication architectures.  

This book first presents the characteristics of the NoC design (topologies, structures, routers, wrappers, and protocols), as well as a summary of the terms used in the field and an overview of the existing industrial and academic NoCs. Secondly, the main aspects of the test of a NoC-based system are discussed, starting with the test of the embedded cores where the NoC plays an important role. Current test strategies are presented, such as the reuse of the network for core testing, test scheduling for the NoC reuse, test access methods and interface, efficient reuse of the network, and power-aware and thermal aware NoC-based SoC testing. Then, the challenges and solutions for the NoC infrastructure (interconnects, routers, and network interface) test and diagnosis are presented. Finally, fault tolerance techniques for the NoC are discussed, including techniques based on error control coding, retransmission, fault location, and system reconfiguration.

  • Provides state-of-the-art research on the challenges to test, diagnose and tolerate faults in NoC-based systems;
  • Includes numerous, current test strategies, including re-use of the network for core testing, test scheduling for the NoC reuse, test access methods and interface, efficient re-use of the network, and power-aware and thermal-aware NoC-based SoC testing; 
  • Offers a single source reference to the latest research, otherwise available only in disparate journals and conference proceedings.

 
 
 
 

 

Keywords

  • Design for Test
  • Electronics Testing
  • Embedded Systems
  • Fault Tolerance
  • Network on Chip
  • Network-on-Chip Testing
  • On-Chip Communication Architectures
  • Power Aware Test
  • System-on-Chip
  • System-on-Chip Testing
  • Thermal Aware Test

Authors and Affiliations

  • Instituto de Informática, Porto Alegre, Brazil

    Érika Cota

  • PUCRS, Faculdade de Informática, Hardware Design Support Group (GAPH), Porto Alegre, Brazil

    Alexandre Morais Amory

  • CEITEC SA, Porto Alegre, Brazil

    Marcelo Soares Lubaszewski

Bibliographic Information

  • Book Title: Reliability, Availability and Serviceability of Networks-on-Chip

  • Authors: Érika Cota, Alexandre Morais Amory, Marcelo Soares Lubaszewski

  • DOI: https://doi.org/10.1007/978-1-4614-0791-1

  • Publisher: Springer New York, NY

  • eBook Packages: Engineering, Engineering (R0)

  • Copyright Information: Springer Science+Business Media, LLC 2012

  • Hardcover ISBN: 978-1-4614-0790-4

  • Softcover ISBN: 978-1-4899-7350-4

  • eBook ISBN: 978-1-4614-0791-1

  • Edition Number: 1

  • Number of Pages: XIII, 209

  • Topics: Electronic Circuits and Systems, Computer-Aided Engineering (CAD, CAE) and Design

Buying options

eBook
USD 89.00
Price excludes VAT (USA)
  • ISBN: 978-1-4614-0791-1
  • Instant PDF download
  • Readable on all devices
  • Own it forever
  • Exclusive offer for individuals only
  • Tax calculation will be finalised during checkout
Softcover Book
USD 119.99
Price excludes VAT (USA)
Hardcover Book
USD 149.99
Price excludes VAT (USA)