Software Synthesis from Dataflow Graphs

  • Shuvra S. Battacharyya
  • Praveen K. Murthy
  • Edward A. Lee

Part of the The Kluwer International Series in Engineering and Computer Science book series (SECS, volume 360)

Table of contents

  1. Front Matter
    Pages i-xi
  2. Shuvra S. Battacharyya, Praveen K. Murthy, Edward A. Lee
    Pages 1-27
  3. Shuvra S. Battacharyya, Praveen K. Murthy, Edward A. Lee
    Pages 29-36
  4. Shuvra S. Battacharyya, Praveen K. Murthy, Edward A. Lee
    Pages 37-56
  5. Shuvra S. Battacharyya, Praveen K. Murthy, Edward A. Lee
    Pages 57-92
  6. Shuvra S. Battacharyya, Praveen K. Murthy, Edward A. Lee
    Pages 93-118
  7. Shuvra S. Battacharyya, Praveen K. Murthy, Edward A. Lee
    Pages 119-140
  8. Shuvra S. Battacharyya, Praveen K. Murthy, Edward A. Lee
    Pages 141-160
  9. Shuvra S. Battacharyya, Praveen K. Murthy, Edward A. Lee
    Pages 161-167
  10. Shuvra S. Battacharyya, Praveen K. Murthy, Edward A. Lee
    Pages 169-174
  11. Back Matter
    Pages 175-189

About this book

Introduction

Software Synthesis from Dataflow Graphs addresses the problem of generating efficient software implementations from applications specified as synchronous dataflow graphs for programmable digital signal processors (DSPs) used in embedded real- time systems. The advent of high-speed graphics workstations has made feasible the use of graphical block diagram programming environments by designers of signal processing systems. A particular subset of dataflow, called Synchronous Dataflow (SDF), has proven efficient for representing a wide class of unirate and multirate signal processing algorithms, and has been used as the basis for numerous DSP block diagram-based programming environments such as the Signal Processing Workstation from Cadence Design Systems, Inc., COSSAP from Synopsys® (both commercial tools), and the Ptolemy environment from the University of California at Berkeley.
A key property of the SDF model is that static schedules can be determined at compile time. This removes the overhead of dynamic scheduling and is thus useful for real-time DSP programs where throughput requirements are often severe. Another constraint that programmable DSPs for embedded systems have is the limited amount of on-chip memory. Off-chip memory is not only expensive but is also slower and increases the power consumption of the system; hence, it is imperative that programs fit in the on-chip memory whenever possible.
Software Synthesis from Dataflow Graphs reviews the state-of-the-art in constructing static, memory-optimal schedules for programs expressed as SDF graphs. Code size reduction is obtained by the careful organization of loops in the target code. Data buffering is optimized by constructing the loop hierarchy in provably optimal ways for many classes of SDF graphs. The central result is a uniprocessor scheduling framework that provably synthesizes the most compact looping structures, called single appearance schedules, for a certain class of SDF graphs. In addition, algorithms and heuristics are presented that generate single appearance schedules optimized for data buffering usage. Numerous practical examples and extensive experimental data are provided to illustrate the efficacy of these techniques.

Keywords

Overhead Signal Software algorithms computer-aided design (CAD) consumption digital signal processor embedded systems model programming signal processing signal processor

Authors and affiliations

  • Shuvra S. Battacharyya
    • 1
  • Praveen K. Murthy
    • 2
  • Edward A. Lee
    • 2
  1. 1.Hitachi America, Ltd.USA
  2. 2.University of CaliforniaBerkeleyUSA

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4613-1389-2
  • Copyright Information Springer-Verlag US 1996
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4612-8601-1
  • Online ISBN 978-1-4613-1389-2
  • Series Print ISSN 0893-3405
  • Buy this book on publisher's site