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A Unified Approach for Timing Verification and Delay Fault Testing

  • Mukund Sivaraman
  • Andrzej J. Strojwas

Table of contents

  1. Front Matter
    Pages i-xv
  2. Mukund Sivaraman, Andrzej J. Strojwas
    Pages 1-6
  3. Mukund Sivaraman, Andrzej J. Strojwas
    Pages 7-39
  4. Mukund Sivaraman, Andrzej J. Strojwas
    Pages 41-57
  5. Mukund Sivaraman, Andrzej J. Strojwas
    Pages 59-81
  6. Mukund Sivaraman, Andrzej J. Strojwas
    Pages 83-106
  7. Mukund Sivaraman, Andrzej J. Strojwas
    Pages 107-126
  8. Mukund Sivaraman, Andrzej J. Strojwas
    Pages 127-137
  9. Back Matter
    Pages 139-155

About this book

Introduction

Large system complexities and operation under tight timing constraints in rapidly shrinking technologies have made it extremely important to ensure correct temporal behavior of modern-day digital circuits, both before and after fabrication. Research in (pre-fabrication) timing verification and (post-fabrication) delay fault testing has evolved along largely disjoint lines in spite of the fact that they share many basic concepts.
A Unified Approach for Timing Verification and Delay Fault Testing applies concepts developed in the context of delay fault testing to path sensitization, which allows an accurate timing analysis mechanism to be developed. This path sensitization strategy is further applied for efficient delay fault diagnosis and delay fault coverage estimation.
A new path sensitization strategy called Signal Stabilization Time Analysis (SSTA) has been developed based on the fact that primitive PDFs determine the stabilization time of the circuit outputs. This analysis has been used to develop a feasible method of identifying the primitive PDFs in a general multi-level logic circuit. An approach to determine the maximum circuit delay using this primitive PDF identification mechanism is also presented. The Primitive PDF Identification-based Timing Analysis (PITA) approach is proved to determine the maximum floating mode circuit delay exactly under any component delay model, and provides several advantages over previously floating mode timing analyzers.
A framework for the diagnosis of circuit failures caused by distributed path delay faults is also presented. A metric to quantify the diagnosability of a path delay fault for a test is also proposed. Finally, the book presents a very realistic metric for delay fault coverage which accounts for delay fault size distributions and is applicable to any delay fault model.
A Unified Approach for Timing Verification and Delay Fault Testing will be of interest to university and industry researchers in timing analysis and delay fault testing as well as EDA tool development engineers and design verification engineers dealing with timing issues in ULSI circuits.
The book should also be of interest to digital designers and others interested in knowing the state of the art in timing verification and delay fault testing.

Keywords

PDF Signal calculus development diagnosis digital design logic mechanism model tables testing verification

Authors and affiliations

  • Mukund Sivaraman
    • 1
  • Andrzej J. Strojwas
    • 1
  1. 1.Carnegie Mellon UniversityPittsburghUSA

Bibliographic information