Skip to main content

Minimizing and Exploiting Leakage in VLSI Design

  • Book
  • © 2010

Overview

  • Provides a variety of approaches to control and exploit leakage
  • Examines the issues with implementing sub-threshold logic and describes techniques to tackle these issues
  • Presents a new, practical self-compensated, closed loop approach to controlling leakage, via sub-threshold circuits, which yields upwards of 20X power savings

This is a preview of subscription content, log in via an institution to check access.

Access this book

eBook USD 89.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book USD 119.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Other ways to access

Licence this eBook for your library

Institutional subscriptions

Table of contents (16 chapters)

  1. Leakage Reduction Techniques: Minimizing Leakage in Modern Day DSM Processes

  2. Leakage Reduction Techniques: Minimizing Leakage In Modern Day DSM Processes

  3. Practical Methodologies for Sub-threshold Circuit Design: Exploiting Leakage Through Sub-threshold Circuit Design

  4. Design of a Sub-threshold BFSK Transmitter IC

  5. Design of a Sub-threshold BFSK Transmitter IC

Keywords

About this book

Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents two techniques aimed at reducing leakage power in digital VLSI ICs. The first technique reduces leakage through the selective use of high threshold voltage sleep transistors. The second technique reduces leakage by applying the optimal Reverse Body Bias (RBB) voltage. This book also shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic.

Authors and Affiliations

  • Sunnyvale, U.S.A.

    Nikhil Jayakumar

  • Austin, U.S.A.

    Suganth Paul

  • Hillsboro, U.S.A.

    Rajesh Garg

  • College Station, U.S.A.

    Kanupriya Gulati

  • Dept. Electrical & Computer Engineering, Texas A & M University, College Station, U.S.A.

    Sunil P. Khatri

Bibliographic Information

  • Book Title: Minimizing and Exploiting Leakage in VLSI Design

  • Authors: Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri

  • DOI: https://doi.org/10.1007/978-1-4419-0950-3

  • Publisher: Springer New York, NY

  • eBook Packages: Engineering, Engineering (R0)

  • Copyright Information: Springer-Verlag US 2010

  • Hardcover ISBN: 978-1-4419-0949-7Published: 03 December 2009

  • Softcover ISBN: 978-1-4899-8529-3Published: 28 November 2014

  • eBook ISBN: 978-1-4419-0950-3Published: 02 December 2009

  • Edition Number: 1

  • Number of Pages: XXVII, 214

  • Topics: Circuits and Systems, Computer-Aided Engineering (CAD, CAE) and Design

Publish with us