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Minimizing and Exploiting Leakage in VLSI Design

  • Nikhil Jayakumar
  • Suganth Paul
  • Rajesh Garg
  • Kanupriya Gulati
  • Sunil P. Khatri

Table of contents

  1. Front Matter
    Pages 1-22
  2. Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri
    Pages 1-6
  3. Leakage Reduction Techniques: Minimizing Leakage in Modern Day DSM Processes

    1. Front Matter
      Pages 7-8
    2. Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri
      Pages 9-14
    3. Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri
      Pages 15-31
    4. Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri
      Pages 33-54
    5. Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri
      Pages 55-76
    6. Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri
      Pages 77-90
    7. Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri
      Pages 91-100
    8. Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri
      Pages 101-105
  4. Practical Methodologies for Sub-threshold Circuit Design: Exploiting Leakage Through Sub-threshold Circuit Design

    1. Front Matter
      Pages 107-108
    2. Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri
      Pages 109-114
    3. Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri
      Pages 115-128
    4. Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri
      Pages 129-142
    5. Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri
      Pages 143-155
    6. Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri
      Pages 157-159
  5. Design of a Sub-threshold BFSK Transmitter IC

    1. Front Matter
      Pages 161-162
    2. Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri
      Pages 163-175
    3. Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri
      Pages 177-191
    4. Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati, Sunil P. Khatri
      Pages 193-199
  6. Back Matter
    Pages 1-13

About this book

Introduction

Minimizing and Exploiting Leakage in VLSI Design

Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati and Sunil P. Khatri

Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs.

This book presents techniques aimed at reducing and exploiting leakage power in digital VLSI ICs. The first part of this book presents several approaches to reduce leakage in a circuit. The second part of this book shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic, with adaptive body bias to make the designs robust to variations. The third part of this book presents design and implementation details of a sub-threshold IC, using the ideas presented in the second part of this book.

  • Provides a variety of approaches to control and exploit leakage, including implicit approaches to find the leakage of all input vectors in a design, techniques to find the minimum leakage vector of a design (with and without circuit modification), ASIC approaches to drastically reduce leakage, and methods to find the optimal reverse bias voltage to maximally reduce leakage.
  • Presents a variation-tolerant, practical design methodology to implement sub-threshold logic using closed-loop adaptive body bias (ABB) and Network of PLA (NPLA) based design. In addition, asynchronous micropipelining techniques are presented, to substantially reclaim the speed penalty of sub-threshold design.
  • Validates the proposed ABB and NPLA sub-threshold design approach by implementing a BFSK transmitter design in the proposed design style. Test results from the fabricated IC are provided as well, indicating that a power improvement of 20X can be obtained for a 0.25um process (projected power improvements are 100X to 500X for 65nm processes).

Keywords

ASIC EDA Electronic Design Automation Leakage Low Power Design Sub-threshold logic Transistor VLSI VLSI Design integrated circuit

Authors and affiliations

  • Nikhil Jayakumar
    • 1
  • Suganth Paul
    • 2
  • Rajesh Garg
    • 3
  • Kanupriya Gulati
    • 4
  • Sunil P. Khatri
    • 5
  1. 1.SunnyvaleU.S.A.
  2. 2.AustinU.S.A.
  3. 3.HillsboroU.S.A.
  4. 4.College StationU.S.A.
  5. 5.Dept. Electrical & Computer EngineeringTexas A & M UniversityCollege StationU.S.A.

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4419-0950-3
  • Copyright Information Springer Science+Business Media, LLC 2010
  • Publisher Name Springer, Boston, MA
  • eBook Packages Engineering
  • Print ISBN 978-1-4419-0949-7
  • Online ISBN 978-1-4419-0950-3
  • Buy this book on publisher's site