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  • Book
  • Open Access
  • © 2013

Intel Xeon Phi Coprocessor Architecture and Tools

The Guide for Application Developers

Apress

Authors:

  • Intel® Xeon Phi™ Coprocessor Architecture and Tools: The Guide for Application Developers provides developers a comprehensive introduction and in-depth look at the Intel Xeon Phi coprocessor architecture and the corresponding parallel data structure tools and algorithms used in technical computing applications.

Buying options

Softcover Book USD 9.99 USD 29.99
67% discount Price excludes VAT (USA)

Table of contents (14 chapters)

  1. Front Matter

    Pages i-xxi
  2. Hardware Foundation: Intel Xeon Phi Architecture

    1. Front Matter

      Pages 1-1
    2. Introduction to Xeon Phi Architecture

      • Rezaur Rahman
      Pages 3-14Open Access
    3. Programming Xeon Phi

      • Rezaur Rahman
      Pages 15-30Open Access
    4. Xeon Phi Vector Architecture and Instruction Set

      • Rezaur Rahman
      Pages 31-48Open Access
    5. Xeon Phi Core Microarchitecture

      • Rezaur Rahman
      Pages 49-64Open Access
    6. Xeon Phi Cache and Memory Subsystem

      • Rezaur Rahman
      Pages 65-80Open Access
    7. Xeon Phi PCIe Bus Data Transfer and Power Management

      • Rezaur Rahman
      Pages 81-94Open Access
  3. Software Foundation: Intel Xeon Phi System Software and Tools

    1. Front Matter

      Pages 95-95
    2. Xeon Phi System Software

      • Rezaur Rahman
      Pages 97-112Open Access
    3. Xeon Phi Application Development Tools

      • Rezaur Rahman
      Pages 113-136Open Access
  4. Applications: Technical Computing Software Development on Intel Xeon Phi

    1. Front Matter

      Pages 137-137
    2. Xeon Phi Application Design and Implementation Considerations

      • Rezaur Rahman
      Pages 139-152Open Access
    3. Application Performance Tuning on Xeon Phi

      • Rezaur Rahman
      Pages 153-170Open Access
    4. Algorithm and Data Structures for Xeon Phi

      • Rezaur Rahman
      Pages 171-184Open Access
    5. Xeon Phi Application Development on Windows OS

      • Rezaur Rahman
      Pages 185-194Open Access
    6. OpenCL on Xeon Phi

      • Rezaur Rahman
      Pages 195-198Open Access
    7. Virtual Shared Memory Programming on Xeon Phi

      • Rezaur Rahman
      Pages 199-202Open Access
  5. Back Matter

    Pages 203-209

About this book

Intel® Xeon Phi™ Coprocessor Architecture and Tools: The Guide for Application Developers provides developers a comprehensive introduction and in-depth look at the Intel Xeon Phi coprocessor architecture and the corresponding parallel data structure tools and algorithms used in the various technical computing applications for which it is suitable. It also examines the source code-level optimizations that can be performed to exploit the powerful features of the processor.

Xeon Phi is at the heart of world’s fastest commercial supercomputer, which thanks to the massively parallel computing capabilities of Intel Xeon Phi processors coupled with Xeon Phi coprocessors attained 33.86 teraflops of benchmark performance in 2013. Extracting such stellar performance in real-world applications requires a sophisticated understanding of the complex interaction among hardware components, Xeon Phi cores, and the applications running on them.

In this book, Rezaur Rahman, an Intel leader in the development of the Xeon Phi coprocessor and the optimization of its applications, presents and details all the features of Xeon Phi core design that are relevant to the practice of application developers, such as its vector units, hardware multithreading, cache hierarchy, and host-to-coprocessor communication channels. Building on this foundation, he shows developers how to solve real-world technical computing problems by selecting, deploying, and optimizing the available algorithms and data structure alternatives matching Xeon Phi’s hardware characteristics. From Rahman’s practical descriptions and extensive code examples, the reader will gain a working knowledge of the Xeon Phi vector instruction set and the Xeon Phi microarchitecture whereby cores execute 512-bit instruction streams in parallel.

About the author

Rezaur Rahmanis a Senior Staff Engineer in the Intel Software and Services Group. He played a key role in the inception and development of the Xeon Phi coprocessor for technical computing applications by demonstrating the viability of applying Intel s manycore graphics processor codenamed Larrabee to solving technical computing problems. He led the worldwide technical enabling team for Intel Xeon Phi products, focused on porting and optimizing applications on the Xeon Phi coprocessor for hundreds of technical computing customers. He has worked internally with hardware architects and Intel compiler and tools teams to optimize and add features to improve the performance of Intel Many Integrated Core (MIC) and Xeon Phi software and hardware components. With 25 years experience in computer architecture and software design, Rahman contributes his expertise in technical code optimization, performance tuning, and hardware microarchitectural analysis in the HPC domain to various industry standardization groups such as the World Wide Web Consortium (W3C). Rahman holds a master s degree in computer science from Texas A&M University and a bachelor s in electrical engineering from Bangladesh University of Engineering and Technology.

Bibliographic Information

Buying options

Softcover Book USD 9.99 USD 29.99
67% discount Price excludes VAT (USA)