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Table of contents

  1. Front Matter
    Pages i-xxi
  2. Hardware Foundation: Intel Xeon Phi Architecture

    1. Front Matter
      Pages 1-1
    2. Rezaur Rahman
      Pages 3-14 Open Access
    3. Rezaur Rahman
      Pages 15-30 Open Access
    4. Rezaur Rahman
      Pages 31-48 Open Access
    5. Rezaur Rahman
      Pages 49-64 Open Access
    6. Rezaur Rahman
      Pages 65-80 Open Access
    7. Rezaur Rahman
      Pages 81-94 Open Access
  3. Software Foundation: Intel Xeon Phi System Software and Tools

    1. Front Matter
      Pages 95-95
    2. Rezaur Rahman
      Pages 97-112 Open Access
    3. Rezaur Rahman
      Pages 113-136 Open Access
  4. Applications: Technical Computing Software Development on Intel Xeon Phi

    1. Front Matter
      Pages 137-137
    2. Rezaur Rahman
      Pages 139-152 Open Access
    3. Rezaur Rahman
      Pages 153-170 Open Access
    4. Rezaur Rahman
      Pages 171-184 Open Access
    5. Rezaur Rahman
      Pages 185-194 Open Access
    6. Rezaur Rahman
      Pages 195-198
    7. Rezaur Rahman
      Pages 199-202
  5. Back Matter
    Pages 203-209

About this book

Introduction

Intel® Xeon Phi™ Coprocessor Architecture and Tools: The Guide for Application Developers provides developers a comprehensive introduction and in-depth look at the Intel Xeon Phi coprocessor architecture and the corresponding parallel data structure tools and algorithms used in the various technical computing applications for which it is suitable. It also examines the source code-level optimizations that can be performed to exploit the powerful features of the processor.

Xeon Phi is at the heart of world’s fastest commercial supercomputer, which thanks to the massively parallel computing capabilities of Intel Xeon Phi processors coupled with Xeon Phi coprocessors attained 33.86 teraflops of benchmark performance in 2013. Extracting such stellar performance in real-world applications requires a sophisticated understanding of the complex interaction among hardware components, Xeon Phi cores, and the applications running on them.

In this book, Rezaur Rahman, an Intel leader in the development of the Xeon Phi coprocessor and the optimization of its applications, presents and details all the features of Xeon Phi core design that are relevant to the practice of application developers, such as its vector units, hardware multithreading, cache hierarchy, and host-to-coprocessor communication channels. Building on this foundation, he shows developers how to solve real-world technical computing problems by selecting, deploying, and optimizing the available algorithms and data structure alternatives matching Xeon Phi’s hardware characteristics. From Rahman’s practical descriptions and extensive code examples, the reader will gain a working knowledge of the Xeon Phi vector instruction set and the Xeon Phi microarchitecture whereby cores execute 512-bit instruction streams in parallel.

Bibliographic information