Table of contents

  1. Front Matter
    Pages i-xi
  2. R. J. Mitchell
    Pages 1-21
  3. R. J. Mitchell
    Pages 22-33
  4. R. J. Mitchell
    Pages 34-84
  5. R. J. Mitchell
    Pages 85-107
  6. R. J. Mitchell
    Pages 108-161
  7. R. J. Mitchell
    Pages 162-174
  8. R. J. Mitchell
    Pages 175-190
  9. Back Matter
    Pages 191-218

About this book

Introduction

The IEEE approved STE bus is the newest bus standard to be introduced to ensure efficient and reliable communication between microprocessors and related devices. After introducing bus systems, the author gives a survey of buses. This is followed by detailed interfacing of slave devices to STE, with practical circuits. Other typical slave devices are then discussed. The various ways in which one or many microprocessors and other bus masters may be connected to STE are described. Testing, software, practical aspects of digital circuitry and technical requirements of the STE specification are then considered. Finally, algorithms for the design of sequential logic circuits are presented.

Keywords

algorithms boundary element method communication computer design Logic microprocessor processor requirement requirements software testing

Authors and affiliations

  • R. J. Mitchell
    • 1
  1. 1.Department of CyberneticsThe University of ReadingUK

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-349-10972-2
  • Copyright Information Macmillan Publishers Limited 1989
  • Publisher Name Palgrave, London
  • eBook Packages Engineering
  • Print ISBN 978-0-333-49649-7
  • Online ISBN 978-1-349-10972-2
  • About this book