VLSI-SoC: From Systems to Silicon

1. Front Matter

   Pages i-x

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2. Molecular Electronics – Devices and Circuits Technology

   • Paul Franzon, David Nackashi, Christian Amsinck, Neil DiSpigna, Sachin Sonkusale

   Pages 1-10

3. Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals

   • Fraidy Bouesse, Marc Renaudin, Gilles Sicard

   Pages 11-24

4. A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures

   • Leonardo L. de Oliveira, Cristiano Santos, Daniel Ferrão, Eduardo Costa, José Monteiro, João Baptista Martins et al.

   Pages 25-39

5. Defragmentation Algorithms for Partially Reconfigurable Hardware

   • Markus Koester, Heiko Kalte, Mario Porrmann, Ulrich Rückert

   Pages 41-53

6. Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits

   • Bertrand Folco, Vivian Brégier, Laurent Fesquet, Marc Renaudin

   Pages 55-69

7. 3D-SoftChip: A Novel 3D Vertically Integrated Adaptive Computing System

   • Chul Kim, Alex Rassau, Stefan Lachowicz, Saeid Nooshabadi, Kamran Eshraghian

   Pages 71-86

8. Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems on FPGA Platforms

   • Alberto Donato, Fabrizio Ferrandi, Massimo Redaelli, Marco Domenico Santambrogio, Donatella Sciuto

   Pages 87-109

9. A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on a-priori Functional Fault- Tolerance Analysis

   • Milos Stanisavljevic, Alexandre Schmid, Yusuf Leblebici

   Pages 111-125

10. Issues in Model Reduction of Power Grids

    • João M. S. Silva, L. Miguel Silveira

    Pages 127-144

11. A Traffic Injection Methodology with Support for System-Level Synchronization

    • Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen

    Pages 145-161

12. Pareto Points in SRAM Design Using the Sleepy Stack Approach

    • Jun Cheol Park, Vincent J. Mooney III

    Pages 163-177

13. Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs

    • César A. M. Marcon, José C. S. Palma, Ney L. V. Calazans, Fernando G. Moraes, Altamiro A. Susin, Ricardo Reis

    Pages 179-194

14. Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping

    • Jérôme Quartana, Laurent Fesquet, Marc Renaudin

    Pages 195-207

15. A Novel MicroPhotonic Structure for Optical Header Recognition

    • Muhsen Aljada, Kamal Alameh, Adam Osseiran, Khalid Al-Begain

    Pages 209-219

16. Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint

    • Erik Larsson, Stina Edbom

    Pages 221-244

17. On-chip Pseudorandom Testing for Linear and Nonlinear MEMS

    • Achraf Dhayni, Salvador Mir, Libor Rufer, Ahcène Bounceur

    Pages 245-266

18. Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles

    • N. Badereddine, P. Girard, S. Pravossoudovitch, A. Virazel, C. Landrault

    Pages 267-281

19. On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction

    • Thilo Pionteck, Thomas Stiefmeier, Thorsten Staake, Manfred Glesner

    Pages 283-297

20. Exact BDD Minimization for Path-Related Objective Functions

    • Rüdiger Ebendt, Rolf Drechsler

    Pages 299-315

This book contains extended and revised versions of the best papers that were presented during the thirteenth edition of the IFIP TC10/WG10.5 International Conference on Very Large Scale Integration, a Global System-on-a-Chip Design & CAD conference. The 13th conference was held at the Parmelia Hilton Hotel, Perth, Western Australia (October 17-19, 2005). Previous conferences have taken place in Edinburgh, Trondheim, Vancouver, Munich, Grenoble, Tokyo, Gramado, Lisbon, Montpellier and Darmstadt. The purpose of this conference, sponsored by IFIP TC 10 Working Group 10.5, is to provide a forum to exchange ideas and show industrial and academic research results in the field of mic- electronics design. The current trend toward increasing chip integ- tion and technology process advancements brings about stimulating new challenges both at the physical and system-design levels, as well in the test of these systems. VLSI-SOC conferences aim to address these exciting new issues. The 2005 edition of VLSI-SoC maintained the traditional structure, which has been successful at the previous VLSI-SOC conferences. The quality of submissions (107 papers from 26 countries) made the selection process difficult, but finally 63 papers and 25 posters were accepted for presentation in VLSI-SoC 2005. Out of the 63 full papers presented at the conference, 20 were chosen by a selection committee to have an extended and revised version included in this book. These selected papers came from Australia, Brazil, France, Germany, Italy, Korea, Portugal, Sweden, Switzerland, United Kingdom and the United States of America. x Preface

• Field Programmable Gate Array
• circuit
• system on chip (SoC)
• testing
• transistor

• Federal University of Rio Grande do Sul, PPGC – GME, Agronomia, Brazil

  Ricardo Reis

• Edith Cowan University, Joondalup, Australia

  Adam Osseiran

• ULM University, Germany

  Hans-Joerg Pfleiderer