Overview
- Provides practical implementation guidelines for the practicing engineer
- Explains key decisions that need to be made in implementing low power designs, why they were made and what results were obtained in actual silicon
- Describes test chips and methods jointly developed by Synopsys and ARM
- Includes supplementary material: sn.pub/extras
Part of the book series: Integrated Circuits and Systems (ICIR)
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Table of contents (14 chapters)
Keywords
About this book
“Tools alone aren't enough to reduce dynamic and leakage power in complex chip designs - a well-planned methodology is needed. Following in the footsteps of the successful Reuse Methodology Manual (RMM), authors from ARM and Synopsys have written this Low Power Methodology Manual (LPMM) to describe [such] [a] low-power methodology with a practical, step-by-step approach.”
Richard Goering, Software Editor, EE Times
“Excellent compendium of low-power techniques and guidelines with balanced content spanning theory and practical implementation. The LPMM is a very welcome addition to the field of low power SoC implementation that has for many years operated in a largely ad-hoc fashion.”
Sujeeth Joseph, Chief Architect - Semiconductor and Systems Solutions Unit, Wipro Technologies
“The LPMM enables broader adoption of aggressive power management techniques based on extensive experience and silicon example with real data that every SOC designer can use to meet the difficulties faced in managing the power issues in deep submicron designs.”
Anil Mankar, Sr VP Worldwide Core Engineering and Chief Development Officer, Conexant Systems Inc.
“Managing power, at 90nm and below, introduces significant challenges to design flow. The LPMM is a timely and immediately useful book that shows how combination of tools, IP and methodology can be used together to address power management.”
Nick Salter, Head of Chip Integration, CSR plc.
Authors and Affiliations
About the authors
ABOUT THE AUTHORS:
Michael Keating is a Synopsys Fellow in the company’s Advanced Technology Group, focusing on IP development methodology, hardware and software design quality and low power design.
David Flynn is an ARM R&D Fellow and has been with the company since 1991, specializing in low power System-on-Chip IP deployment and methodology.
Robert Aitken is an ARM R&D Fellow. His areas of responsibility include memory architecture, design for testability and design for manufacturability.
Alan Gibbons is a Principal Engineer at Synopsys, with a focus on development of advanced methodology and technology for ARM processor-based system design.
Kaijian Shi is a Principal Consultant in the Professional Services Group of Synopsys, specializing in low power design methodology and implementation.
Bibliographic Information
Book Title: Low Power Methodology Manual
Book Subtitle: For System-on-Chip Design
Authors: Michael Keating, David Flynn, Robert Aitken, Alan Gibbons, Kaijian Shi
Series Title: Integrated Circuits and Systems
DOI: https://doi.org/10.1007/978-0-387-71819-4
Publisher: Springer New York, NY
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer-Verlag US 2007
Hardcover ISBN: 978-0-387-71818-7Published: 31 July 2007
Softcover ISBN: 978-1-4419-4418-4Published: 26 May 2011
eBook ISBN: 978-0-387-71819-4Published: 31 July 2007
Series ISSN: 1558-9412
Series E-ISSN: 1558-9420
Edition Number: 1
Number of Pages: XVI, 300
Topics: Circuits and Systems, Electronics and Microelectronics, Instrumentation, Electrical Engineering, Computer Hardware