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Creating Assertion-Based IP

  • Harry D. Foster
  • Adam C. Krolnik

Table of contents

  1. Front Matter
    Pages i-xviii
  2. Pages 1-17
  3. Pages 37-57
  4. Pages 63-112
  5. Pages 113-143
  6. Pages 145-175
  7. Pages 177-252
  8. Back Matter
    Pages 253-313

About this book

Introduction

Assertion-based IP is much more than a comprehensive set of related assertions. It is a full-fledged reusable and configurable transaction-level verification component, which is used to detect both interesting and incorrect behaviors. Upon detecting interesting or incorrect behavior, the assertion-based IP alerts other verification components within a simulation environment, which are responsible for taking appropriate action. The focus of this book is to bring the assertion discussion up to a higher level and introduce a process for creating effective, reusable, assertion-based IP, which easily integrates with the user’s existing verification environment, in other words the testbench infrastructure.

The guiding principles promoted in this book when creating an assertion-based IP monitor are:

  • modularity—assertion-based IP should have a clear separation between detection and action

  • clarity—assertion-based IP should be written initially focusing on capturing intent (versus optimizations)

A unique feature of this book is the fully worked out, detailed examples. The concepts presented in the book are drawn from the authors’ experience developing assertion-based IP, as well as general assertion-based techniques. Creating Assertion-Based IP is an important resource for design and verification engineers.

From the Foreword:

Creating Assertion-Based IP "…reduces to process the creation of one of the most valuable kinds of VIP: assertion-based VIP…This book will serve as a valuable reference for years to come."

Andrew Piziali, Sr. Design Verification Engineer
Co-Author, ESL Design and Verification: A Prescription for Electronic System Level Methodology
Author, Functional Verification Coverage Measurement and Analysis

Keywords

Assertion-Based Foster Krolnik SystemVerilog Verification Verilog integrated circuits optimization simulation

Authors and affiliations

  • Harry D. Foster
    • 1
  • Adam C. Krolnik
    • 2
  1. 1.Mentor GraphicsPlanoUSA
  2. 2.LSI Logic CorporationAllenUSA

Bibliographic information

  • DOI https://doi.org/10.1007/978-0-387-68398-0
  • Copyright Information Springer Science+Business Media, LLC 2008
  • Publisher Name Springer, Boston, MA
  • eBook Packages Engineering
  • Print ISBN 978-0-387-36641-8
  • Online ISBN 978-0-387-68398-0
  • Buy this book on publisher's site