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Computer Aided Verification

Fourth International Workshop, CAV '92, Montreal, Canada, June 29 - July 1, 1992. Proceedings

  • Conference proceedings
  • © 1993

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Editors:
  1. Gregor Bochmann
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  2. David Karl Probst
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Part of the book series: Lecture Notes in Computer Science (LNCS, volume 663)

Included in the following conference series:

Conference proceedings info: CAV 1992.

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About this book

This volume gives the proceedings of the Fourth Workshop on Computer-Aided Verification (CAV '92), held in Montreal, June 29 - July 1, 1992. The objective of this series of workshops is to bring together researchers and practitioners interested in the development and use of methods, tools and theories for the computer-aided verification of concurrent systems. The workshops provide an opportunity for comparing various verification methods and practical tools that can be used to assist the applications designer. Emphasis is placed on new research results and the application of existing results to real verification problems. The volume contains 31 papers selected from 75 submissions. These are organized into parts on reduction techniques, proof checking, symbolic verification, timing verification, partial-order approaches, case studies, model and proof checking, and other approaches. The volume starts with an invited lectureby Leslie Lamport entitled "Computer-hindered verification (humans can do it too)".

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Table of contents (32 papers)

  1. Front Matter

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  2. Computer-hindered verification (humans can do it too)

    • Leslie Lamport
    Pages 1-1

  3. Modular abstractions for verifying real-time distributed systems

    • Hana De-Leon, Orna Grumberg
    Pages 2-15

  4. Layering techniques for development of parallel systems

    • Mannes Poel, Job Zwiers
    Pages 16-29

  5. Efficient local correctness checking

    • Kim Guldstrand Larsen
    Pages 30-43

  6. Mechanical verification of concurrent systems with TLA

    • Urban Engberg, Peter Grønning, Leslie Lamport
    Pages 44-55

  7. Using a theorem prover for reasoning about concurrent algorithms

    • Joakim von Wright, Thomas Långbacka
    Pages 56-68

  8. Verifying a logic synthesis tool in Nuprl: A case study in software verification

    • Mark Aagaard, Miriam Leeser
    Pages 69-81

  9. Higher-level specification and verification with BDDs

    • Alan J. Hu, David L. Dill, Andreas J. Drexler, C. Han Yang
    Pages 82-95

  10. Symbolic bisimulation minimisation

    • Amar Bouali, Robert de Simone
    Pages 96-108

  11. Towards a verification technique for large synchronous circuits

    • Prabhat Jain, Prabhakar Kudva, Ganesh Gopalakrishnan
    Pages 109-122

  12. Verifying timed behavior automata with nonbinary delay constraints

    • David K. Probst, Hon F. Li
    Pages 123-136

  13. Timing verification by successive approximation

    • R. Alur, A. Itai, R. Kurshan, M. Yannakakis
    Pages 137-150

  14. A verification strategy for timing constrained systems

    • Felice Balarin, Alberto L. Sangiovanni-Vincentelli
    Pages 151-163

  15. Using unfoldings to avoid the state explosion problem in the verification of asynchronous circuits

    • K. L. McMillan
    Pages 164-177

  16. State space caching revisited

    • Patrice Godefroid, Gerard J. Holzmann, Didier Pirottin
    Pages 178-191

  17. Verification in process algebra of the distributed control of track vehicles—A case study

    • Siegfried Fischer, Andreas Scholz, Dirk Taubner
    Pages 192-205

  18. Design verification of a microprocessor using branching time regular temporal logic

    • Kiyoharu Hamaguchi, Hiromi Hiraishi, Shuzo Yajima
    Pages 206-219

  19. A case study in safety-critical design

    • Glenn Bruns
    Pages 220-233

  20. Automatic reduction in CTL compositional model checking

    • Thomas R. Shiple, Massimiliano Chiodo, Alberto L. Sangiovanni-Vincentelli, Robert K. Brayton
    Pages 234-247
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