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Intelligent Memory Systems

Second InternationalWorkshop, IMS 2000 Cambridge, MA, USA, November 12, 2000 Revised Papers

  • Frederic T. Chong
  • Christoforos Kozyrakis
  • Mark Oskin
Conference proceedings IMS 2000

Part of the Lecture Notes in Computer Science book series (LNCS, volume 2107)

Table of contents

  1. Front Matter
    Pages I-VIII
  2. Memory Technology

    1. Hiroshi Nakamura, Masaaki Kondo, Taisuke Boku
      Pages 15-32
  3. Processor and Memory Architecture

    1. Robert Cooksey, Dennis Colarelli, Dirk Grunwald
      Pages 33-55
    2. Lixin Zhang, Venkata K. Pingali, Bharat Chandramouli, John B. Carter
      Pages 56-70
    3. Yan Solihin, Jaejin Lee, Joseph Torrellas
      Pages 71-84
  4. Applications and Operating Systems

    1. Richard C. Murphy, Peter M. Kogge, Arun Rodrigues
      Pages 85-103
    2. Mary Hall, Craig Steele
      Pages 104-121
  5. Compiler Technology

    1. David Judd, Katherine Yelick, Christoforos Kozyrakis, David Martin, David Patterson
      Pages 122-134
    2. Csaba Andras Moritz, Matthew I. Frank, Saman Amarasinghe
      Pages 135-146
  6. Poster Session

    1. Peter Grun, Nikil Dutt, Alex Nicolau
      Pages 147-151
    2. Michael Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas
      Pages 152-159
    3. Tsung-Chuan Huang, Slo-Li Chu
      Pages 160-168
    4. Dan Nicolaescu, Xiaomei Ji, Alexander Veidenbaum, Alexandru Nicolau, Rajesh Gupta
      Pages 183-187
  7. Back Matter
    Pages 193-193

About these proceedings

Introduction

We are pleased to present this collection of papers from the Second Workshop on Intelligent Memory Systems. Increasing die densities and inter chip communication costs continue to fuel interest in intelligent memory systems. Since the First Workshop on Mixing Logic and DRAM in 1997, technologies and systems for computation in memory have developed quickly. The focus of this workshop was to bring together researchers from academia and industry to discuss recent progress and future goals. The program committee selected 8 papers and 6 poster session abstracts from 29 submissions for inclusion in the workshop. Four to five members of the program committee reviewed each submission and their reviews were used to numerically rank them and guide the selection process. We believe that the resulting program is of the highest quality and interest possible. The selected papers cover a wide range of research topics such as circuit technology, processor and memory system architecture, compilers, operating systems, and applications. They also present a mix of mature projects, work in progress, and new research ideas. The workshop also included two invited talks. Dr. Subramanian Iyer (IBM Microelectronics) provided an overview of embedded memory technology and its potential. Dr. Mark Snir (IBM Research) presented the Blue Gene, an aggressive supercomputer system based on intelligent memory technology.

Keywords

Distributed Architectures Intelligent Memory Architectures Intelligent Memory Systems Inter-Chip Communication Memory Architecture Memory Management On-Chip Memory PIM Architectures Processor Architecture Reconfigurable Memory compiler operating system

Editors and affiliations

  • Frederic T. Chong
    • 1
  • Christoforos Kozyrakis
    • 2
  • Mark Oskin
    • 1
  1. 1.Dept. of Computer ScienceUniversity of CaliforniaDavisUSA
  2. 2.EECS Computer Science DivisionUniversity of CaliforniaBerkeleyUSA

Bibliographic information

  • DOI https://doi.org/10.1007/3-540-44570-6
  • Copyright Information Springer-Verlag Berlin Heidelberg 2001
  • Publisher Name Springer, Berlin, Heidelberg
  • eBook Packages Springer Book Archive
  • Print ISBN 978-3-540-42328-7
  • Online ISBN 978-3-540-44570-8
  • Series Print ISSN 0302-9743
  • Buy this book on publisher's site