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Correct Hardware Design and Verification Methods

13th IFIP WG 10.5Advanced Research, Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings

  • Conference proceedings
  • © 2005

Overview

Editors:
  1. Dominique Borrione

    1. TIMA Laboratory, VDS Group, Grenoble, France

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    You can also search for this editor in PubMed   Google Scholar

  2. Wolfgang Paul

    1. Computer Science Dept., Saarland University, Saarbrücken, Germany

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    You can also search for this editor in PubMed   Google Scholar

Part of the book series: Lecture Notes in Computer Science (LNCS, volume 3725)

Part of the book sub series: Theoretical Computer Science and General Issues (LNTCS)

Included in the following conference series:

Conference proceedings info: CHARME 2005.

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Table of contents (42 papers)

  1. Front Matter

    Download chapter PDF

  3. Tutorial

    1. Towards the Pervasive Verification of Automotive Systems

      • Thomas In der Rieden, Dirk Leinenbach, Wolfgang Paul
      Pages 3-4

  4. Functional Approaches to Design Description

    1. Wired: Wire-Aware Circuit Design

      • Emil Axelsson, Koen Claessen, Mary Sheeran
      Pages 5-19

    2. Formalization of the DE2 Language

      • Warren A. Hunt Jr., Erik Reeber
      Pages 20-34

  5. Game Solving Approaches

    1. Finding and Fixing Faults

      • Stefan Staber, Barbara Jobstmann, Roderick Bloem
      Pages 35-49

    2. Verifying Quantitative Properties Using Bound Functions

      • Arindam Chakrabarti, Krishnendu Chatterjee, Thomas A. Henzinger, Orna Kupferman, Rupak Majumdar
      Pages 50-64

  6. Abstraction

    1. How Thorough Is Thorough Enough?

      • Arie Gurfinkel, Marsha Chechik
      Pages 65-80

    2. Interleaved Invariant Checking with Dynamic Abstraction

      • Liang Zhang, Mukul R. Prasad, Michael S. Hsiao
      Pages 81-96

    3. Automatic Formal Verification of Liveness for Pipelined Processors with Multicycle Functional Units

      • Miroslav N. Velev
      Pages 97-113

  7. Algorithms and Techniques for Speeding (DD-Based) Verification 1

    1. Efficient Symbolic Simulation via Dynamic Scheduling, Don’t Caring, and Case Splitting

      • Viresh Paruthi, Christian Jacobi, Kai Weber
      Pages 114-128

    2. Achieving Speedups in Distributed Symbolic Reachability Analysis Through Asynchronous Computation

      • Orna Grumberg, Tamir Heyman, Nili Ifergan, Assaf Schuster
      Pages 129-145

    3. Saturation-Based Symbolic Reachability Analysis Using Conjunctive and Disjunctive Partitioning

      • Gianfranco Ciardo, Andy Jinqing Yu
      Pages 146-161

  8. Real Time and LTL Model Checking

    1. Real-Time Model Checking Is Really Simple

      • Leslie Lamport
      Pages 162-175

    2. Temporal Modalities for Concisely Capturing Timing Diagrams

      • Hana Chockler, Kathi Fisler
      Pages 176-190

    3. Regular Vacuity

      • Doron Bustan, Alon Flaisher, Orna Grumberg, Orna Kupferman, Moshe Y. Vardi
      Pages 191-206

  9. Algorithms and Techniques for Speeding Verification 2

    1. Automatic Generation of Hints for Symbolic Traversal

      • David Ward, Fabio Somenzi
      Pages 207-221

    2. Maximal Input Reduction of Sequential Netlists via Synergistic Reparameterization and Localization Strategies

      • Jason Baumgartner, Hari Mony
      Pages 222-237

    3. A New SAT-Based Algorithm for Symbolic Trajectory Evaluation

      • Jan-Willem Roorda, Koen Claessen
      Pages 238-253
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Other volumes

  1. Correct Hardware Design and Verification Methods

Editors and Affiliations

  • TIMA Laboratory, VDS Group, Grenoble, France

    Dominique Borrione

  • Computer Science Dept., Saarland University, Saarbrücken, Germany

    Wolfgang Paul

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