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Field Programmable Logic and Application

14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings

  • Conference proceedings
  • © 2004

Overview

Editors:
  1. Jürgen Becker

    1. ITIV - Universitaet Karlsruhe (TH),  

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  2. Marco Platzner

    1. University of Paderborn,  

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    You can also search for this editor in PubMed   Google Scholar

  3. Serge Vernalde

    1. IMEC, Leuven, Belgium

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Part of the book series: Lecture Notes in Computer Science (LNCS, volume 3203)

Included in the following conference series:

Conference proceedings info: FPL 2004.

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Table of contents (177 papers)

  1. Architectures 2

    1. Reconfigurable Instruction Set Extension for Enabling ECC on an 8-Bit Processor

      • Sandeep Kumar, Christof Paar
      Pages 586-595

  2. Memory 2

    1. Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors

      • Miljan Vuletić, Laura Pozzi, Paolo Ienne
      Pages 596-605

    2. Storage Allocation for Diverse FPGA Memory Specifications

      • Dalia Dagher, Iyad Ouaiss
      Pages 606-616

  3. Image Processing 1

    1. Real Time Optical Flow Processing System

      • Javier Díaz, Eduardo Ros, Sonia Mota, Richard Carrillo, Rodrigo Agis
      Pages 617-626

    2. Methods and Tools for High-Resolution Imaging

      • Tim Todman, Wayne Luk
      Pages 627-636

  4. Network-on-Chip

    1. Network-on-Chip for Reconfigurable Systems: From High-Level Design Down to Implementation

      • T. A. Bartic, D. Desmet, J-Y. Mignolet, T. Marescaux, D. Verkest, S. Vernalde et al.
      Pages 637-647

    2. A Reconfigurable Recurrent Bitonic Sorting Network for Concurrently Accessible Data

      • Christophe Layer, Hans-Jörg Pfleiderer
      Pages 648-657

  6. IP-Based Design

    1. HW/SW Co-design by Automatic Embedding of Complex IP Cores

      • Holger Lange, Andreas Koch
      Pages 679-689

    2. Increasing Pipelined IP Core Utilization in Process Networks Using Exploration

      • Claudiu Zissulescu, Bart Kienhuis, Ed Deprettere
      Pages 690-699

    3. Distribution of Bitstream-Level IP Cores for Functional Evaluation Using FPGAs

      • Rawat Siripokarpirom
      Pages 700-709

    4. SOC and RTOS: Managing IPs and Tasks Communications

      • Arthur Segard, François Verdier
      Pages 710-718

  7. Power Aware Design 2

    1. The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays

      • Steven J. E. Wilton, Su-Shin Ang, Wayne Luk
      Pages 719-728

    2. A Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms

      • Jingzhao Ou, Viktor K. Prasanna
      Pages 729-739

    3. Power-Driven Design Partitioning

      • Rajarshi Mukherjee, Seda Ogrenci Memik
      Pages 740-750

    4. Power Consumption Reduction Through Dynamic Reconfiguration

      • Michael G. Lorenz, Luis Mengibar, Mario G. Valderas, Luis Entrena
      Pages 751-760

  8. Coprocessing Architectures

    1. The XPP Architecture and Its Co-simulation Within the Simulink Environment

      • M. Petrov, T. Murgan, F. May, M. Vorbach, P. Zipf, M. Glesner
      Pages 761-770

    2. An FPGA Based Coprocessor for the Classification of Tissue Patterns in Prostatic Cancer

      • M. A. Tahir, A. Bouridane, F. Kurugollu
      Pages 771-780

    3. Increasing ILP of RISC Microprocessors Through Control-Flow Based Reconfiguration

      • Steffen Köhler, Jens Braunes, Thomas Preußer, Martin Zabel, Rainer G. Spallek
      Pages 781-790
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Editors and Affiliations

  • ITIV - Universitaet Karlsruhe (TH),  

    Jürgen Becker

  • University of Paderborn,  

    Marco Platzner

  • IMEC, Leuven, Belgium

    Serge Vernalde

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