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  • Conference proceedings
  • © 2004

Field Programmable Logic and Application

14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings

Editors:

  1. Jürgen Becker

    1. ITIV - Universitaet Karlsruhe (TH),  

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  2. Marco Platzner

    1. University of Paderborn,  

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    You can also search for this editor in PubMed   Google Scholar

  3. Serge Vernalde

    1. IMEC, Leuven, Belgium

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Part of the book series: Lecture Notes in Computer Science (LNCS, volume 3203)

Conference series link(s): FPL: International Conference on Field Programmable Logic and Applications

Conference proceedings info: FPL 2004.

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Table of contents (177 papers)

  1. Signal Processing 1

    1. Area*Time Optimized Hogenauer Channelizer Design Using FPL Devices

      • Uwe Meyer-Bäse, Suhasini Rao, Javier Ramírez, Antonio García
      Pages 384-393

    2. A Steerable Complex Wavelet Construction and Its Implementation on FPGA

      • C. -S. Bouganis, P. Y. K. Cheung, J. Ng, A. A. Bharath
      Pages 394-403

  2. Computational Models and Compiler

    2. JHDLBits: The Merging of Two Worlds

      • Alexandra Poetter, Jesse Hunter, Cameron Patterson, Peter Athanas, Brent Nelson, Neil Steiner
      Pages 414-423

    3. A System Level Resource Estimation Tool for FPGAs

      • Changchun Shi, James Hwang, Scott McMillan, Ann Root, Vinay Singh
      Pages 424-433

    4. The PowerPC Backend Molen Compiler

      • Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis
      Pages 434-443

  3. Dynamic Reconfiguration 1

    1. An Integrated Online Scheduling and Placement Methodology

      • Manish Handa, Ranga Vemuri
      Pages 444-453

    2. On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities

      • Michael Ullmann, Michael Hübner, Björn Grimm, Jürgen Becker
      Pages 454-463

    3. Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor – An Approach to Tough Cases –

      • Hideharu Amano, Takeshi Inuo, Hirokazu Kami, Taro Fujii, Masayasu Suzuki
      Pages 464-473

  4. Network and Optimization Algorithms

    1. Over 10Gbps String Matching Mechanism for Multi-stream Packet Scanning Systems

      • Yutaka Sugawara, Mary Inaba, Kei Hiraki
      Pages 484-493

    2. Hardware Design of a FPGA-Based Synchronizer for Hiperlan/2

      • Ma José Canet, Felip Vicedo, Vicenç Almenar, Javier Valls, Eduardo R. de Lima
      Pages 494-504

    3. Three-Dimensional Dynamic Programming for Homology Search

      • Yoshiki Yamaguchi, Tsutomu Maruyama, Akihiko Konagaya
      Pages 505-515

    4. An Instance-Specific Hardware Algorithm for Finding a Maximum Clique

      • Shin’ichi Wakabayashi, Kenji Kikuchi
      Pages 516-525

  5. System-on-Chip 1

    1. IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter

      • Ralf Ludewig, Oliver Soffke, Peter Zipf, Manfred Glesner, Kong Pang Pun, Kuen Hung Tsoi et al.
      Pages 526-535

    2. Automatic Creation of Reconfigurable PALs/PLAs for SoC

      • Mark Holland, Scott Hauck
      Pages 536-545

  6. High Speed Design

    1. A Key Agile 17.4 Gbit/sec Camellia Implementation

      • Daniel Denning, James Irvine, Malachy Devlin
      Pages 546-554

    2. High Performance True Random Number Generator in Altera Stratix FPLDs

      • Viktor Fischer, Miloš Drutarovský, Martin Šimka, Nathalie Bochard
      Pages 555-564

  7. Security and Cryptography 2

    1. A Universal and Efficient AES Co-processor for Field Programmable Logic Arrays

      • Norbert Pramstaller, Johannes Wolkerstorfer
      Pages 565-574

    2. Exploring Area/Delay Tradeoffs in an AES FPGA Implementation

      • Joseph Zambreno, David Nguyen, Alok Choudhary
      Pages 575-585
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Editors and Affiliations

  • ITIV - Universitaet Karlsruhe (TH),  

    Jürgen Becker

  • University of Paderborn,  

    Marco Platzner

  • IMEC, Leuven, Belgium

    Serge Vernalde

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