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Field Programmable Logic and Application

14th International Conference, FPL 2004, Leuven, Belgium, August 30-September 1, 2004. Proceedings

  • Jürgen Becker
  • Marco Platzner
  • Serge Vernalde
Conference proceedings FPL 2004

Part of the Lecture Notes in Computer Science book series (LNCS, volume 3203)

Table of contents

  1. Front Matter
    PDF

  2. Plenary Keynotes

    1. FPGAs and the Era of Field Programmability
      Wim Roelandts
      Pages 1-1
    2. Reconfigurable Systems Emerge
      Nick Tredennick, Brion Shimamoto
      Pages 2-11
    3. System-Level Design Tools Can Provide Low Cost Solutions in FPGAs: TRUE or FALSE?
      Mark Dickinson
      Pages 12-12

  3. Organic and Biology Computing

    1. Hardware Accelerated Novel Protein Identification
      Anish Alex, Jonathan Rose, Ruth Isserlin-Weinberger, Christopher Hogue
      Pages 13-22
    2. Large Scale Protein Sequence Alignment Using FPGA Reprogrammable Logic Devices
      Stefan Dydel, Piotr Bała
      Pages 23-32

  4. Security and Cryptography 1

    1. A Key Management Architecture for Securing Off-Chip Data Transfers
      Jonathan Graf, Peter Athanas
      Pages 33-42
    2. FPGA Implementation of Biometric Authentication System Based on Hand Geometry
      Celia López-Ongil, Raul Sanchez-Reillo, Judith Liu-Jimenez, Fernando Casado, Leslie Sánchez, Luis Entrena
      Pages 43-53

  5. Platform Based Design

    1. SoftSONIC: A Customisable Modular Platform for Video Applications
      Tero Rissa, Peter Y. K. Cheung, Wayne Luk
      Pages 54-63
    2. Deploying Hardware Platforms for SoC Validation: An Industrial Case Study
      A. Bigot, F. Charpentier, H. Krupnova, I. Sans
      Pages 64-73

  6. Algorithms and Architectures

    1. Algorithms and Architectures for Use in FPGA Implementations of Identity Based Encryption Schemes
      Tim Kerins, Emanuel Popovici, William Marnane
      Pages 74-83
    2. Power Analysis Attacks Against FPGA Implementations of the DES
      François-Xavier Standaert, Sıddıka Berna Örs, Jean-Jacques Quisquater, Bart Preneel
      Pages 84-94

  7. Acceleration Application 1

    1. Monte Carlo Radiative Heat Transfer Simulation on a Reconfigurable Computer
      Maya Gokhale, Janette Frigo, Christine Ahrens, Justin L. Tripp, Ron Minnich
      Pages 95-104
    2. Stochastic Simulation for Biochemical Reactions on FPGA
      M. Yoshimi, Y. Osana, T. Fukushima, H. Amano
      Pages 105-114

  8. Architecture 1

    1. Dynamic Adaptive Runtime Routing Techniques in Multigrain Reconfigurable Hardware Architectures
      Alexander Thomas, Juergen Becker
      Pages 115-124
    2. Interconnecting Heterogeneous Nodes in an Adaptive Computing Machine
      Frederick Furtek, Eugene Hogenauer, James Scheuermann
      Pages 125-134
    3. Improving FPGA Performance and Area Using an Adaptive Logic Module
      Mike Hutton, Jay Schleicher, David Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu et al.
      Pages 135-144
    4. A Dual-VDD Low Power FPGA Architecture
      A. Gayasen, K. Lee, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, T. Tuan
      Pages 145-157

  9. Physical Design 1

    1. Simultaneous Timing Driven Clustering and Placement for FPGAs
      Gang Chen, Jason Cong
      Pages 158-167
    2. Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis
      Jason Anderson, Sudip Nag, Kamal Chaudhary, Sandor Kalman, Chari Madabhushi, Paul Cheng
      Pages 168-178
    3. Compact Buffered Routing Architecture
      A. Lodi, R. Giansante, C. Chiesa, L. Ciccarelli, F. Campi, M. Toma
      Pages 179-188
    4. On Optimal Irregular Switch Box Designs
      Hongbing Fan, Yu-Liang Wu, Chak-Chung Cheung, Jiping Liu
      Pages 189-199

  10. Arithmetic 1

    1. Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation
      Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides
      Pages 200-208
    2. Comparative Study of SRT-Dividers in FPGA
      Gustavo Sutter, Gery Bioul, Jean-Pierre Deschamps
      Pages 209-220
    3. Second Order Function Approximation Using a Single Multiplication on FPGAs
      Jérémie Detrey, Florent de Dinechin
      Pages 221-230
    4. Efficient Modular Division Implementation
      Guerric Meurice de Dormale, Philippe Bulens, Jean-Jacques Quisquater
      Pages 231-240

  11. Multitasking

    1. A Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management
      Jesus Tabero, Julio Septién, Hortensia Mecha, Daniel Mozos
      Pages 241-250
    2. The Partition into Hypercontexts Problem for Hyperreconfigurable Architectures
      Sebastian Lange, Martin Middendorf
      Pages 251-260

  12. Circuit Technology

    1. A High-Density Optically Reconfigurable Gate Array Using Dynamic Method
      Minoru Watanabe, Fuminori Kobayashi
      Pages 261-269
    2. Evolvable Hardware for Signal Separation and Noise Cancellation Using Analog Reconfigurable Device
      D. Keymeulen, R. Zebulum, A. Stoica, V Duong, M. I. Ferguson
      Pages 270-278

  13. Memory 1

    1. Implementing High-Speed Double-Data Rate (DDR) SDRAM Controllers on FPGA
      Eduardo Picatoste-Olloqui, Francisco Cardells-Tormo, Jordi Sempere-Agullo, Atilà Herms-Berenguer
      Pages 279-288
    2. Logic Modules with Shared SRAM Tables for Field-Programmable Gate Arrays
      Fatih Kocan, Jason Meyer
      Pages 289-300

  14. Network Processing

    1. A Modular System for FPGA-Based TCP Flow Processing in High-Speed Networks
      David V. Schuehler, John W. Lockwood
      Pages 301-310
    2. Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs
      Zachary K. Baker, Viktor K. Prasanna
      Pages 311-321

  15. Testing

    1. BIST Based Interconnect Fault Location for FPGAs
      Nicola Campregher, Peter Y. K. Cheung, Milan Vasilko
      Pages 322-332
    2. FPGAs BIST Evaluation
      A. Parreira, J. P. Teixeira, M. B. Santos
      Pages 333-343

  16. Applications

    1. Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor
      C. J. Tavares, C. Bungardean, G. M. Matos, J. T. de Sousa
      Pages 344-353
    2. Evaluating Fault Emulation on FPGA
      Peeter Ellervee, Jaan Raik, Valentin Tihhomirov, Kalle Tammemäe
      Pages 354-363

  17. Arithmetic 2

    1. Automating Optimized Table-with-Polynomial Function Evaluation for FPGAs
      Dong-U Lee, Oskar Mencer, David J. Pearce, Wayne Luk
      Pages 364-373
    2. Multiple Restricted Multiplication
      Nalin Sidahao, George A. Constantinides, Peter Y. K. Cheung
      Pages 374-383

  18. Signal Processing 1

    1. Area*Time Optimized Hogenauer Channelizer Design Using FPL Devices
      Uwe Meyer-Bäse, Suhasini Rao, Javier Ramírez, Antonio García
      Pages 384-393
    2. A Steerable Complex Wavelet Construction and Its Implementation on FPGA
      C. -S. Bouganis, P. Y. K. Cheung, J. Ng, A. A. Bharath
      Pages 394-403

  19. Computational Models and Compiler

    1. Programmable Logic Has More Computational Power than Fixed Logic
      Gordon Brebner
      Pages 404-413
    2. JHDLBits: The Merging of Two Worlds
      Alexandra Poetter, Jesse Hunter, Cameron Patterson, Peter Athanas, Brent Nelson, Neil Steiner
      Pages 414-423
    3. A System Level Resource Estimation Tool for FPGAs
      Changchun Shi, James Hwang, Scott McMillan, Ann Root, Vinay Singh
      Pages 424-433
    4. The PowerPC Backend Molen Compiler
      Elena Moscu Panainte, Koen Bertels, Stamatis Vassiliadis
      Pages 434-443

  20. Dynamic Reconfiguration 1

    1. An Integrated Online Scheduling and Placement Methodology
      Manish Handa, Ranga Vemuri
      Pages 444-453
    2. On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities
      Michael Ullmann, Michael Hübner, Björn Grimm, Jürgen Becker
      Pages 454-463
    3. Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor – An Approach to Tough Cases –
      Hideharu Amano, Takeshi Inuo, Hirokazu Kami, Taro Fujii, Masayasu Suzuki
      Pages 464-473
    4. Throughput and Reconfiguration Time Trade-Offs: From Static to Dynamic Reconfiguration in Dedicated Image Filters
      Marcos R. Boschetti, Sergio Bampi, Ivan S. Silva
      Pages 474-483

About these proceedings

Keywords

Alignment Computer Java SoC algorithms cryptographic implementations field-programmable logic logic operating system optimization power-aware design reconfigurable computing reconfigurable logic system-on-chip systems level design

Editors and affiliations

  • Jürgen Becker
    • 1
  • Marco Platzner
    • 2
  • Serge Vernalde
    • 3
  1. 1.ITIV - Universitaet Karlsruhe (TH) 
  2. 2.University of Paderborn 
  3. 3.IMECLeuvenBelgium

Bibliographic information

  • DOI https://doi.org/10.1007/b99787
  • Copyright Information Springer-Verlag Berlin Heidelberg 2004
  • Publisher Name Springer, Berlin, Heidelberg
  • eBook Packages Springer Book Archive
  • Print ISBN 978-3-540-22989-6
  • Online ISBN 978-3-540-30117-2
  • Series Print ISSN 0302-9743
  • Series Online ISSN 1611-3349
  • Buy this book on publisher's site