Guide to RISC Processors

for Programmers and Engineers

  • Sivarama P. Dandamudi

Table of contents

  1. Front Matter
    Pages i-xv
  2. Overview

    1. Pages 3-11
    2. Pages 39-44
  3. Architectures

    1. Pages 47-54
    2. Pages 55-77
    3. Pages 79-96
    4. Pages 97-120
    5. Pages 121-145
  4. MIPS Assembly Language

    1. Pages 183-210
    2. Pages 211-224
    3. Pages 225-242
    4. Pages 243-267
    5. Pages 291-304
  5. Back Matter
    Pages 323-387

About this book

Introduction

Recently, there has been a trend toward processor design based on the RISC (Reduced Instruction Set Computer) model: Example RISC processors are the MIPS, SPARC, PowerPC, ARM, and even Intel’s 64-bit processor Itanium.

This guidebook provides an accessible and all-encompassing compendium on RISC processors, introducing five RISC processors: MIPS, SPARC, PowerPC, ARM, and Itanium. Initial chapters explain the differences between the CISC and RISC designs and clearly discuss the core RISC design principles. The text then integrates instruction on MIPS assembly language programming, thereby enabling readers to concretely grasp concepts and principles introduced earlier. Readers need only have a basic knowledge of any structured, high-level language to obtain the full benefits here.

Features:

*Includes MIPS simulator (SPIM) download instructions, so that readers can get hands-on assembly language programming experience

*Presents material in a manner suitable for flexible self-study

• Assembly language programs permit reader executables using the SPIM simulator

• Integrates core concepts to processor designs and their implementations

• Supplies extensive and complete programming examples and figures

• Contains chapter-by-chapter overviews and summaries

* Provides source code for the MIPS language at the book’s website

Guide to RISC Processors provides a uniquely comprehensive introduction and guide to RISC-related concepts, principles, design philosophy, and actual programming, as well as the all the popular modern RISC processors and their assembly language. Professionals, programmers, and students seeking an authoritative and practical overview of RISC processors and assembly language programming will find the guide an essential resource.

Sivarama P. Dandamudi is a professor of computer science at Carleton University in Ottawa, Ontario, Canada, as well as associate editor responsible for computer architecture at the International Journal of Computers and Their Applications. He has more than two decades of experience teaching about computer systems and organization. 

 

Key Topics

* Processor design issues

* Evolution of CISC and RISC processors

* MIPS, SPARC, PowerPC, Itanium, and ARM architectures

* MIPS assembly language

* SPIM simulator and debugger

* Conditional execution

* Floating-point and logical and shift operations

* Number systems

 

 

Computer Architecture/Programming

Beginning/Intermediate Level

Keywords

Assembly language CISC MIPS Processor architecture Reduced Instruction Set Computer architecture computer computer architecture design download language processor programming

Authors and affiliations

  • Sivarama P. Dandamudi
    • 1
  1. 1.School of Computer ScienceCarleton UniversityOttawaCanada

Bibliographic information

  • DOI https://doi.org/10.1007/b139084
  • Copyright Information Springer Science+Business Media, Inc. 2005
  • Publisher Name Springer, New York, NY
  • eBook Packages Computer Science
  • Print ISBN 978-0-387-21017-9
  • Online ISBN 978-0-387-27446-1
  • About this book