© 2002

System-on-a-Chip Verification

Methodology and Techniques


Table of contents

  1. Front Matter
    Pages i-xx
  2. Pages 1-43
  3. Pages 153-234
  4. Back Matter
    Pages 361-372

About this book


System-On-a-Chip Verification: Methodology and Techniques is the first book to cover verification strategies and methodologies for SOC verification from system level verification to the design sign- off. The topics covered include Introduction to the SOC design and verification aspects, System level verification in brief, Block level verification, Analog/mixed signal simulation, Simulation, HW/SW Co-verification, Static netlist verification, Physical verification, and Design sign-off in brief. All the verification aspects are illustrated with a single reference design for Bluetooth application.
System-On-a-Chip Verification: Methodology and Techniques takes a systematic approach that covers the following aspects of verification strategy in each chapter:
  1. Explanation of the objective involved in performing verification after a given design step;
  2. Features of options available;
  3. When to use a particular option;
  4. How to select an option; and
  5. Limitations of the option.
This exciting new book will be of interest to all designers and test professionals.


Bluetooth FPGA Field Programmable Gate Array Hardware Signal Software analog calculus design integrated circuit model model checking simulation system on chip (SoC) verification

Authors and affiliations

  1. 1.Cadence Design Systems, Inc.USA

Bibliographic information