Closing the Gap Between ASIC & Custom

Tools and Techniques for High-Performance ASIC Design

  • David Chinnery
  • Kurt Keutzer

Table of contents

  1. Front Matter
    Pages i-xv
  2. David Chinnery, Kurt Keutzer
    Pages 1-31
  3. Contributing Factors

    1. David Chinnery, Kurt Keutzer
      Pages 33-56
    2. David Chinnery, Kurt Keutzer
      Pages 57-100
    3. Andrew Chang, William J. Dally, David Chinnery, Kurt Keutzer, Radu Zlatanovici
      Pages 101-144
    4. David Chinnery, Kurt Keutzer
      Pages 145-168
  4. Design Techniques

    1. Michel Courtoy, Pinhong Chen, Xiaoping Tang, Chin-Chi Teng, Yuji Kukimoto
      Pages 169-186
    2. David Chinnery, Kurt Keutzer, Jagesh Sanghavi, Earl Killian, Kaushik Sheth
      Pages 187-208
    3. Wayne Dai, David Staepelaere
      Pages 209-223
    4. Debashis Bhattacharya, Vamsi Boppana
      Pages 241-267
    5. Stephen E. Rich, Matthew J. Parker, Jim Schwartz
      Pages 305-322
  5. Design Examples

    1. David Chinnery, Borivoje Nikolić, Kurt Keutzer
      Pages 345-360
    2. Nick Richardson, Lun Bin Huang, Razak Hossain, Julian Lewis, Tommy Zounes, Naresh Soni
      Pages 361-381
    3. David Flynn, Michael Keating
      Pages 383-408
  6. Back Matter
    Pages 411-414

About this book


by Kurt Keutzer Those looking for a quick overview of the book should fast-forward to the Introduction in Chapter 1. What follows is a personal account of the creation of this book. The challenge from Earl Killian, formerly an architect of the MIPS processors and at that time Chief Architect at Tensilica, was to explain the significant performance gap between ASICs and custom circuits designed in the same process generation. The relevance of the challenge was amplified shortly thereafter by Andy Bechtolsheim, founder of Sun Microsystems and ubiquitous investor in the EDA industry. At a dinner talk at the 1999 International Symposium on Physical Design, Andy stated that the greatest near-term opportunity in CAD was to develop tools to bring the performance of ASIC circuits closer to that of custom designs. There seemed to be some synchronicity that two individuals so different in concern and character would be pre-occupied with the same problem. Intrigued by Earl and Andy’s comments, the game was afoot. Earl Killian and other veterans of microprocessor design were helpful with clues as to the sources of the performance discrepancy: layout, circuit design, clocking methodology, and dynamic logic. I soon realized that I needed help in tracking down clues. Only at a wonderful institution like the University of California at Berkeley could I so easily commandeer an ab- bodied graduate student like David Chinnery with a knowledge of architecture, circuits, computer-aided design and algorithms.


ASIC Flip-Flop Standard architecture integrated circuit layout logic microprocessor optimization transistor

Authors and affiliations

  • David Chinnery
    • 1
  • Kurt Keutzer
    • 1
  1. 1.University of CaliforniaBerkeley

Bibliographic information