Electromigration Modeling at Circuit Layout Level

  • Cher Ming Tan
  • Feifei He

Part of the SpringerBriefs in Applied Sciences and Technology book series (BRIEFSAPPLSCIENCES)

Also part of the SpringerBriefs in Reliability book sub series (SBR)

Table of contents

  1. Front Matter
    Pages i-x
  2. Cher Ming Tan, Feifei He
    Pages 1-6
  3. Cher Ming Tan, Feifei He
    Pages 7-47
  4. Cher Ming Tan, Feifei He
    Pages 101-103

About this book

Introduction

Integrated circuit (IC) reliability is of increasing concern in present-day IC technology where the interconnect failures significantly increases the failure rate for ICs with decreasing interconnect dimension and increasing number of interconnect levels.  Electromigration (EM) of interconnects has now become the dominant failure mechanism that determines the circuit reliability. This brief addresses the readers to the necessity of 3D real circuit modelling in order to evaluate the EM of interconnect system in ICs, and how they can create such models for their own applications. A 3-dimensional (3D) electro-thermo-structural model as opposed to the conventional current density based 2-dimensional (2D) models is presented at circuit-layout level. 

Keywords

3D Modeling Atomic Flux Divergence (AFD) Circuit Layout Level Electro-thermo-structural Simulations Electromigration (EM) Issues Finite Element Analysis Interconnect Reliability

Authors and affiliations

  • Cher Ming Tan
    • 1
  • Feifei He
    • 2
  1. 1., School of Electrical and Electronic EngrNanyang Technological UniversitySingaporeSingapore
  2. 2.Nanyang Technological UniversitySingaporeSingapore

Bibliographic information

  • DOI https://doi.org/10.1007/978-981-4451-21-5
  • Copyright Information The Author(s) 2013
  • Publisher Name Springer, Singapore
  • eBook Packages Engineering
  • Print ISBN 978-981-4451-20-8
  • Online ISBN 978-981-4451-21-5
  • Series Print ISSN 2191-530X
  • Series Online ISSN 2191-5318
  • About this book