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VLSI Design and Test

22nd International Symposium, VDAT 2018, Madurai, India, June 28-30, 2018, Revised Selected Papers

  • S. Rajaram
  • N.B. Balamurugan
  • D. Gracia Nirmala Rani
  • Virendra Singh
Conference proceedings VDAT 2018

Part of the Communications in Computer and Information Science book series (CCIS, volume 892)

Table of contents

  1. Front Matter
    Pages I-XVIII
    PDF

  2. Digital Design

    1. Front Matter
      Pages 1-1
      PDF
    2. Efficient Hardware-Software Codesigns of AES Encryptor and RS-BCH Encoder
      M. Mohamed Asan Basiri, Sandeep K. Shukla
      Pages 3-15
    3. High Level Synthesis and Implementation of Cryptographic Algorithm in AHIR Platform
      Abhimanniu Raveendran, Sanjay Dhok, Rajendra Patrikar
      Pages 16-27
    4. A Hardware Accelerator for Convolutional Neural Network Using Fast Fourier Transform
      S. Kala, Babita R. Jose, Debdeep Paul, Jimson Mathew
      Pages 28-36
    5. Reconfigurable VLSI-Architecture of Multi-radix Maximum-A-Posteriori Decoder for New Generation of Wireless Devices
      Rahul Shrestha, Ashutosh Sharma
      Pages 37-48
    6. Design of High Speed 5:2 and 7:2 Compressor Using Nanomagnetic Logic
      Shantanu Agarwal, G. Harish, S. Balamurugan, R. Marimuthu
      Pages 49-60
    7. A Comparative Exploration About Approximate Full Adders for Error Tolerant Applications
      M. Priyadharshni, S. Kumaravel
      Pages 61-74

  3. Analog and Mixed Signal Design

    1. Front Matter
      Pages 75-75
      PDF
    2. A PVT Insensitive Low-Power Differential Ring Oscillator
      Nishtha Wadhwa, Pydi Ganga Bahubalindruni, Sujay Deb
      Pages 77-87
    3. Optimal Transistor Sizing of Full-Adder Block to Reduce Standby Leakage Power
      Prateek Gupta, Shubham Kumar, Zia Abbas
      Pages 88-99
    4. A 31 ppm/\(^{\circ }\)C Pure CMOS Bandgap Reference by Exploiting Beta-Multiplier
      R. Nagulapalli, K. Hayatleh, S. Barker, S. Zourob, N. Yassine, B. Naresh Kumar Reddy
      Pages 100-108
    5. Supply and Temperature Independent Voltage Reference Circuit in Subthreshold Region
      Vineysarathi Kokkula, Akash Joshi, Raghvendra Deshmukh
      Pages 109-120
    6. CMOS Implementations of Rectified Linear Activation Function
      P. Priyanka, G. K. Nisarga, S. Raghuram
      Pages 121-129
    7. Voltage Level Adapter Design for High Voltage Swing Applications in CMOS Differential Amplifier
      Ashfakh Ali, Arpan Jain, Zia Abbas
      Pages 130-139
    8. Layout Design of X-Band Low Noise Amplifier for Radar Applications
      I. Stefigraf, S. Rajaram
      Pages 140-156

  4. Hardware Security

    1. Front Matter
      Pages 157-157
      PDF
    2. A Novel Approach to Detect Hardware Malware Using Hamming Weight Model and One Class Support Vector Machine
      P. Saravanan, B. M. Mehtre
      Pages 159-172
    3. Detecting Hardware Trojans by Reducing Rarity of Transitions in ICs
      Tapobrata Dhar, Surajit Kumar Roy, Chandan Giri
      Pages 173-185
    4. Enhanced Logical Locking for a Secured Hardware IP Against Key-Guessing Attacks
      R. Sree Ranjani, M. Nirmala Devi
      Pages 186-197
    5. SARP: Self Aware Runtime Protection Against Integrity Attacks of Hardware Trojans
      Krishnendu Guha, Debasri Saha, Amlan Chakrabarti
      Pages 198-209
    6. A VLSI Architecture for the PRESENT Block Cipher with FPGA and ASIC Implementations
      Jai Gopal Pandey, Tarun Goel, Mausam Nayak, Chhavi Mitharwal, Sajid Khan, Santosh Kumar Vishvakarma et al.
      Pages 210-220
    7. Efficient Data Compression Scheme for Secured Application Needs
      Ravi Kashyap, Twinkle Verma, Priyanka Kwatra, Sidhartha Sankar Rout
      Pages 221-230

  5. Micro Bio-fluidics

    1. Front Matter
      Pages 231-231
      PDF
    2. Effective Method for Temperature Compensation in Dual Band Metal MEMS Resonator
      Amol Morankar, Rajendra Patrikar
      Pages 233-241
    3. Deadlock Detection in Digital Microfluidics Biochip Droplet Routing
      Jyotiranjan Swain, Sumanta Pyne
      Pages 242-253
    4. Fabrication of Molybdenum MEMs Structures Using Dry and Wet Etching
      Sandeep Singh Chauhan, Niharika J, M. M. Joglekar, S. K. Manhas
      Pages 254-263
    5. Continuous Flow Microfluidic Channel Design for Blood Plasma Separation
      Jagriti Srivastava, Rajendra Patrikar
      Pages 264-277
    6. Real Time Mixing Index Measurement of Microchannels Using OpenCV
      Khuushi, Vanadana Jain, Rajendra Patrikar, Raghavendra Deshmukh
      Pages 278-284
    7. Novel RF MEMS Capacitive Switch for Lower Actuation Voltage
      Sagar B. Dhule, Vasu Pulijala
      Pages 285-294

  6. VLSI Testing

    1. Front Matter
      Pages 295-295
      PDF
    2. A Novel Countermeasure Against Differential Scan Attack in AES Algorithm
      Jayesh Popat, Usha Mehta
      Pages 297-309
    3. Optimization of Test Wrapper Length for TSV Based 3D SOCs Using a Heuristic Approach
      Tanusree Kaibartta, Debesh Kumar Das
      Pages 310-321
    4. A Methodology to Design Online Testable Reversible Circuits
      Mrinal Goswami, Govind Raj, Aron Narzary, Bibhash Sen
      Pages 322-334
    5. Robust SRAM Cell Development for Single-Event Multiple Effects
      Naga Raghuram CH, D. Manohar Reddy, Puli Kishore Kumar, Gaurav Kaushal
      Pages 335-347
    6. Automation of Timing Quality Checks and Optimization
      Dubakula Ketavanya, Anand D. Darji
      Pages 348-356

  7. Analog Circuits and Devices

    1. Front Matter
      Pages 357-357
      PDF
    2. Temperature Insensitive Low-Power Ring Oscillator Using only n-type Transistors
      Nishtha Rai, Vaibhav Agarwal, Nishtha Wadhwa, Bhawna Tiwari, Pydi Ganga Bahubalindruni
      Pages 359-369
    3. Low-Power Switched Operational Amplifier Using a-InGaZnO TFTs
      Suprateek Shukla, Bhawna Tiwari, Nishtha Wadhwa, Pydi Ganga Bahubalindruni, Pedro Barquinha
      Pages 370-379
    4. Threshold Voltage Investigation of Recessed Dual-Gate MISHEMT: Simulation Study
      Preeti Singh, Vandana Kumari, Manoj Saxena, Mridula Gupta
      Pages 380-393
    5. LEADER: Leakage Currents Estimation Technique for Aging Degradation Aware 16 nm CMOS Circuits
      Zia Abbas, Andleeb Zahra, Mauro Olivieri
      Pages 394-407
    6. Performance Optimization of FinFET Configurations at 14 nm Technology Using ANN-PSO
      Srishti, Jasmeet Kaur
      Pages 408-417
    7. Performance Analysis of Graphene Based Optical Interconnect at Nanoscale Technology
      Balkrishna Choubey, Vijay Rao Kumbhare, Manoj Kumar Majumder
      Pages 418-429

  8. Network-on-Chip

    1. Front Matter
      Pages 431-431
      PDF
    2. Heuristic Driven Genetic Algorithm for Priority Assignment of Real-Time Communications in NoC
      Ajay Khare, Chinmay Patil, Manikanta Nallamalli, Santanu Chattopadhyay
      Pages 433-445
    3. A Novel Fault-Tolerant Routing Algorithm for Mesh-of-Tree Based Network-on-Chips
      Monil Shah, Mohit Upadhyay, P. Veda Bhanu, J. Soumya, Linga Reddy Cenkeramaddi
      Pages 446-459
    4. Performance Enhancement of NoCs Using Single Cycle Deflection Routers and Adaptive Priority Schemes
      K. S. Midhula, Sarath Babu, John Jose, Sangeetha Jose
      Pages 460-472
    5. 3D LBDR: Logic-Based Distributed Routing for 3D NoC
      Ashish Sharma, Manish Tailor, Lava Bhargava, Manoj Singh Gaur
      Pages 473-482
    6. Parameter Extraction of PSP MOSFET Model Using Particle Swarm Optimization - SoC Approach
      Amit Rathod, Rajesh Thakker
      Pages 483-494
    7. Implementation of a Novel Fault Tolerant Routing Technique for Mesh Network on Chip
      Akshay B. P., Ganesh K. M., Thippeswamy D. R., Vishnu S. Bhat, Anitha Vijayakumar, Ananda Y. R. et al.
      Pages 495-506

About these proceedings

Introduction

This book constitutes the refereed proceedings of the 22st International Symposium on VLSI Design and Test, VDAT 2018, held in Madurai, India, in June 2018.
The 39 full papers and 11 short papers presented together with 8 poster papers were carefully reviewed and selected from 231 submissions. The papers are organized in topical sections named: digital design; analog and mixed signal design; hardware security; micro bio-fluidics; VLSI testing; analog circuits and devices; network-on-chip; memory; quantum computing and NoC; sensors and interfaces.

Keywords

computer hardware computer systems computer networks microprocessor chips signal processing telecommunication systems network protocols

Editors and affiliations

  • S. Rajaram
    • 1
  • N.B. Balamurugan
    • 2
  • D. Gracia Nirmala Rani
    • 3
  • Virendra Singh
    • 4
  1. 1.Thiagarajar College of EngineeringMaduraiIndia
  2. 2.Thiagarajar College of EngineeringMaduraiIndia
  3. 3.Thiagarajar College of EngineeringMaduraiIndia
  4. 4.Indian Institute of Technology BombayMumbaiIndia

Bibliographic information