Design, Analysis and Test of Logic Circuits Under Uncertainty

  • Smita Krishnaswamy
  • Igor L. Markov
  • John P. Hayes

Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 115)

Table of contents

  1. Front Matter
    Pages i-xi
  2. Smita Krishnaswamy, Igor L. Markov, John P. Hayes
    Pages 1-19
  3. Smita Krishnaswamy, Igor L. Markov, John P. Hayes
    Pages 21-36
  4. Smita Krishnaswamy, Igor L. Markov, John P. Hayes
    Pages 37-52
  5. Smita Krishnaswamy, Igor L. Markov, John P. Hayes
    Pages 53-61
  6. Smita Krishnaswamy, Igor L. Markov, John P. Hayes
    Pages 63-91
  7. Smita Krishnaswamy, Igor L. Markov, John P. Hayes
    Pages 93-113
  8. Smita Krishnaswamy, Igor L. Markov, John P. Hayes
    Pages 115-120
  9. Back Matter
    Pages 121-123

About this book

Introduction

Integrated circuits (ICs) increasingly exhibit uncertain characteristics due to soft errors, inherently probabilistic devices, and manufacturing variability. As device technologies scale, these effects can be detrimental to the reliability of logic circuits.  To improve future semiconductor designs, this book describes methods for analyzing, designing, and testing circuits subject to probabilistic effects. The authors first develop techniques to model inherently probabilistic methods in logic circuits and to test circuits for determining their reliability after they are manufactured. Then, they study error-masking mechanisms intrinsic to digital circuits and show how to leverage them to design more reliable circuits.  The book describes techniques for:

 

• Modeling and reasoning about probabilistic behavior in logic circuits, including a matrix-based reliability-analysis framework;

 

• Accurate analysis of soft-error rate (SER) based on functional-simulation, sufficiently scalable for use in gate-level optimizations;

 

• Logic synthesis for greater resilience against soft errors, which improves reliability using moderate overhead in area and performance;

 

• Test-generation and test-compaction methods aimed at probabilistic faults in logic circuits that facilitate accurate and efficient post-manufacture measurement of soft-error susceptibility.

Keywords

Fault-tolerance Probabilistic logic Reliability Soft errors Uncertainty

Authors and affiliations

  • Smita Krishnaswamy
    • 1
  • Igor L. Markov
    • 2
  • John P. Hayes
    • 3
  1. 1., Dept. of Biological SciencesColumbia UniversityNew YorkUSA
  2. 2., Dept. of EECSUniversity of MichiganAnn ArborUSA
  3. 3., Dept. of EECSUniversity of MichiganAnn ArborUSA

Bibliographic information

  • DOI https://doi.org/10.1007/978-90-481-9644-9
  • Copyright Information Springer Science+Business Media Dordrecht 2013
  • Publisher Name Springer, Dordrecht
  • eBook Packages Engineering
  • Print ISBN 978-90-481-9643-2
  • Online ISBN 978-90-481-9644-9
  • Series Print ISSN 1876-1100
  • Series Online ISSN 1876-1119
  • About this book