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Network-on-Chip Architectures

A Holistic Design Exploration

  • Chrysostomos Nicopoulos
  • Vijaykrishnan Narayanan
  • Chita R. Das

Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 45)

Table of contents

  1. Front Matter
    Pages i-xxi
  2. MICRO-Architectural Exploration

    1. Front Matter
      Pages 18-18
    2. Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das
      Pages 1-12
    3. Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das
      Pages 13-16
    4. Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das
      Pages 19-40
    5. Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das
      Pages 65-92
    6. Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das
      Pages 93-115
  3. MACRO-Architectural Exploration

    1. Front Matter
      Pages 118-118
    2. Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das
      Pages 119-146
    3. Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das
      Pages 147-170
    4. Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das
      Pages 171-197
    5. Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das
      Pages 199-205
    6. Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R. Das
      Pages 207-209
  4. Back Matter
    Pages 211-223

About this book

Introduction

The continuing reduction of feature sizes into the nanoscale regime has led to dramatic increases in transistor densities. Integration at these levels has highlighted the criticality of the on-chip interconnects. Network-on-Chip (NoC) architectures are viewed as a possible solution to burgeoning global wiring delays in many-core chips, and have recently crystallized into a significant research domain. On-chip networks instill a new flavor to communication research due to their inherently resource-constrained nature. Despite the lightweight character demanded of the NoC components, modern designs require ultra-low communication latencies in order to cope with inflating data bandwidths. The work presented in Network-on-Chip Architectures addresses these issues through a comprehensive exploration of the design space. The design aspects of the NoC are viewed through a penta-faceted prism encompassing five major issues: (1) performance, (2) silicon area consumption, (3) power/energy efficiency, (4) reliability, and (5) variability. These five aspects serve as the fundamental design drivers and critical evaluation metrics in the quest for efficient NoC implementations. The research exploration employs a two-pronged approach: (a) MICRO-architectural innovations within the major NoC components, and (b) MACRO-architectural choices aiming to seamlessly merge the interconnection backbone with the remaining system modules. These two research threads and the aforementioned five key metrics mount a holistic and in-depth attack on most issues surrounding the design of NoCs in multi-core architectures.

Keywords

Computer Architecture Energy Efficiency Fault Tolerance Network-on-Chip On-Chip Interconnects integrated circuit network on chip (NoC) processor reliability transistor

Authors and affiliations

  • Chrysostomos Nicopoulos
    • 1
  • Vijaykrishnan Narayanan
    • 2
  • Chita R. Das
    • 3
  1. 1.Dept. Electrical & Computer EngineeringUniversity of CyprusNicosiaCyprus
  2. 2.Dept. Computer Science & EngineeringPennsylvania State UniversityUniversity ParkU.S.A.
  3. 3.Dept. Computer Science & EngineeringPennsylvania State UniversityUniversity ParkU.S.A.

Bibliographic information

  • DOI https://doi.org/10.1007/978-90-481-3031-3
  • Copyright Information Springer Science+Business Media B.V. 2010
  • Publisher Name Springer, Dordrecht
  • eBook Packages Engineering
  • Print ISBN 978-90-481-3030-6
  • Online ISBN 978-90-481-3031-3
  • Series Print ISSN 1876-1100
  • Series Online ISSN 1876-1119
  • Buy this book on publisher's site