Book Volume 6760 2011

Transactions on High-Performance Embedded Architectures and Compilers IV

Editors:

ISBN: 978-3-642-24567-1 (Print) 978-3-642-24568-8 (Online)

Table of contents (21 chapters)

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  1. Front Matter

    Pages -

  2. Regular Papers

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      Chapter

      Pages 1-20

      A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors

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      Chapter

      Pages 21-41

      Characterizing Time-Varying Program Behavior Using Phase Complexity Surfaces

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      Chapter

      Pages 42-62

      Compiler Directed Issue Queue Energy Reduction

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      Chapter

      Pages 63-83

      A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors

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      Chapter

      Pages 84-110

      Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors

  3. 4th International Conference on High-Performance and Embedded Architectures and Compilers – HiPEAC (Selected Papers)

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      Chapter

      Pages 111-134

      A Highly Scalable Parallel Implementation of H.264

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      Chapter

      Pages 135-154

      Communication Based Proactive Link Power Management

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      Chapter

      Pages 155-174

      Finding Extreme Behaviors in Microprocessor Workloads

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      Chapter

      Pages 175-194

      Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture

  4. Workshop on Software and Hardware Challenges of Many-core Platforms – SHCMP (Selected Papers)

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      Chapter

      Pages 195-214

      Transaction Reordering to Reduce Aborts in Software Transactional Memory

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      Chapter

      Pages 215-233

      A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture

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      Chapter

      Pages 234-253

      A Modular Simulator Framework for Network-on-Chip Based Manycore Chips Using UNISIM

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      Chapter

      Pages 254-273

      Software Transactional Memory Validation – Time and Space Considerations

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      Chapter

      Pages 274-293

      Tiled Multi-Core Stream Architecture

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      Chapter

      Pages 294-310

      An Efficient and Flexible Task Management for Many Cores

  5. 8th IEEE International Symposium on Systems, Architectures, Modeling and Simulation – SAMOS VIII (Selected Papers)

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      Chapter

      Pages 311-333

      On Two-Layer Brain-Inspired Hierarchical Topologies – A Rent’s Rule Approach –

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      Chapter

      Pages 334-353

      Advanced Packet Segmentation and Buffering Algorithms in Network Processors

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      Chapter

      Pages 354-369

      Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation

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      Chapter

      Pages 370-390

      A Cost Model for Partial Dynamic Reconfiguration

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      Chapter

      Pages 391-408

      Heterogeneous Design in Functional DIF

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