High Performance Embedded Architectures and Compilers

5th International Conference, HiPEAC 2010, Pisa, Italy, January 25-27, 2010. Proceedings

  • Yale N. Patt
  • Pierfrancesco Foglia
  • Evelyn Duesterwald
  • Paolo Faraboschi
  • Xavier Martorell
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5952)

Table of contents

  1. Front Matter
  2. Invited Program

  3. Architectural Support for Concurrency

    1. Henry Hoffmann, David Wentzlaff, Anant Agarwal
      Pages 3-17
    2. Mohammad Ansari, Behram Khan, Mikel Luján, Christos Kotselidis, Chris Kirkham, Ian Watson
      Pages 35-49
    3. Cesare Ferri, Samantha Wood, Tali Moreshet, Iris Bahar, Maurice Herlihy
      Pages 50-65
  4. Compilation and Runtime Systems

    1. Boubacar Diouf, Albert Cohen, Fabrice Rastello, John Cavazos
      Pages 66-80
    2. Olga Golovanevsky, Alon Dayan, Ayal Zaks, David Edelsohn
      Pages 81-95
    3. Paul M. Carpenter, Alex Ramirez, Eduard Ayguadé
      Pages 96-110
    4. Alexander Monakov, Anton Lokhmotov, Arutyun Avetisyan
      Pages 111-125
  5. Reconfigurable and Customized Architectures

    1. Theo Kluter, Samuel Burri, Philip Brisk, Edoardo Charbon, Paolo Ienne
      Pages 126-140
    2. Roger Moussalli, Mariam Salloum, Walid Najjar, Vassilis Tsotras
      Pages 141-155
    3. Rainer Ohlendorf, Michael Meitinger, Thomas Wild, Andreas Herkersdorf
      Pages 156-170
    4. Yongjoo Kim, Jongeun Lee, Aviral Shrivastava, Jonghee Yoon, Yunheung Paek
      Pages 171-185
  6. Multicore Efficiency, Reliability, and Power

    1. Shuguang Feng, Shantanu Gupta, Amin Ansari, Scott Mahlke
      Pages 186-200
    2. Houman Homayoun, Aseem Gupta, Alex Veidenbaum, Avesta Sasan (M.A. Makhzan), Fadi Kurdahi, Nikil Dutt
      Pages 216-231
    3. Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny
      Pages 232-246
  7. Memory Organization and Optimization

About these proceedings

Introduction

This book constitutes the refereed proceedings of the 5th International  Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2010, held in Pisa, Italy, in January 2010.

The 23 revised full papers presented together with the abstracts of 2 invited keynote addresses were carefully reviewed and selected from 94 submissions. The papers are organized in topical sections on architectural support for concurrency; compilation and runtime systems; reconfigurable and customized architectures; multicore efficiency, reliability, and power; memory organization and optimization; and programming and analysis of accelerators.

Keywords

CMP Computer Online Scheduling code compression communication systems compilation compiler optimizations compiler techniques complexity data affinity domain-specific language embedded systems high performance software load balancing

Editors and affiliations

  • Yale N. Patt
    • 1
  • Pierfrancesco Foglia
    • 2
  • Evelyn Duesterwald
    • 3
  • Paolo Faraboschi
    • 4
  • Xavier Martorell
    • 5
  1. 1.Department of Electrical and Computer EngineeringThe University of Texas at AustinAustinUSA
  2. 2.Dipartimento di Ingegneria della InformazioneUniversità di PisaPisaItaly
  3. 3.IBM T.J.Watson Research CenterHawthorneUSA
  4. 4.Hewlett-Packard, Cami de Can Graells 1-21, Sant Cugat del VallésBarcelonaSpain
  5. 5.Computer Architecture DepartmentTechnical University of Catalunya (UPC)BarcelonaSpain

Bibliographic information

  • DOI https://doi.org/10.1007/978-3-642-11515-8
  • Copyright Information Springer-Verlag Berlin Heidelberg 2010
  • Publisher Name Springer, Berlin, Heidelberg
  • eBook Packages Computer Science
  • Print ISBN 978-3-642-11514-1
  • Online ISBN 978-3-642-11515-8
  • Series Print ISSN 0302-9743
  • Series Online ISSN 1611-3349
  • About this book