Transactions on High-Performance Embedded Architectures and Compilers II

  • Per Stenström
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5470)

Table of contents

  1. Front Matter
  2. Special Section on High-Performance Embedded Architectures and Compilers

    1. Front Matter
      Pages 1-1
    2. Per Stenström, David Whalley
      Pages 3-3
    3. Georgios Keramidas, Polychronis Xekalakis, Stefanos Kaxiras
      Pages 4-22
    4. Vijay Nagarajan, Rajiv Gupta, Arvind Krishnaswamy
      Pages 23-44
    5. Major Bhadauria, Sally A. McKee, Karan Singh, Gary S. Tyson
      Pages 65-84
    6. Chunling Hu, Daniel A. Jiménez, Ulrich Kremer
      Pages 85-104
  3. Regular Papers

    1. Front Matter
      Pages 105-105
    2. Woojin Choi, Seok-Jun Park, Michel Dubois
      Pages 107-127
    3. Hans Vandierendonck, André Seznec
      Pages 128-148
    4. Dominique Chanet, Javier Cabezas, Enric Morancho, Nacho Navarro, Koen De Bosschere
      Pages 173-200
    5. Aneesh Aggarwal
      Pages 201-221
    6. Christine Rochange, Pascal Sainrat
      Pages 222-241
    7. Amit Golander, Shlomo Weiss
      Pages 242-268
    8. Arquimedes Canedo, Ben Abderazek, Masahiro Sowa
      Pages 269-285
  4. Back Matter

About this book

Introduction

Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems.

This second issue contains 15 papers carefully reviewed and selected out of 31 submissions and is divided into two sections. The first section contains extended versions of the top five papers from the 2nd International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC 2007) held in Ghent, Belgium, in January 2007.  The second section consists of ten papers covering topics such as microarchitecture, memory systems, code generation, and performance modeling.

Keywords

Action code generation code size reduction compiler compiler techniques computer computer architecture dynamic compilation embedded systems high-performance architecture memory system optimization network processors optimization parallel architectures tar

Editors and affiliations

  • Per Stenström
    • 1
  1. 1.Department of Computer Science and EngineeringChalmers University of TechnologyGothenburgSweden

Bibliographic information

  • DOI https://doi.org/10.1007/978-3-642-00904-4
  • Copyright Information Springer-Verlag Berlin Heidelberg 2009
  • Publisher Name Springer, Berlin, Heidelberg
  • eBook Packages Computer Science
  • Print ISBN 978-3-642-00903-7
  • Online ISBN 978-3-642-00904-4
  • Series Print ISSN 0302-9743
  • Series Online ISSN 1611-3349
  • About this book