Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation

18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers

  • Lars Svensson
  • José Monteiro
Conference proceedings PATMOS 2008

Part of the Lecture Notes in Computer Science book series (LNCS, volume 5349)

Table of contents

  1. Front Matter
  2. Session 1: Low-Leakage and Subthreshold Circuits

    1. Biswajit Mishra, Bashir M. Al-Hashimi
      Pages 1-10
    2. Armin Tajalli, Massimo Alioto, Elizabeth J. Brauer, Yusuf Leblebici
      Pages 21-30
    3. Matteo Agostinelli, Massimo Alioto, David Esseni, Luca Selmi
      Pages 31-41
  3. Session 2: Low-Power Methods and Models

    1. Ashoka Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
      Pages 42-51
    2. Roni Wiener, Gila Kamhi, Moshe Y. Vardi
      Pages 52-61
    3. Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura
      Pages 62-71
    4. Yoni Aizik, Gila Kamhi, Yael Zbar, Hadas Ronen, Muhammad Abozaed
      Pages 72-81
    5. Vasily G. Moshnyaga
      Pages 82-92
  4. Session 3: Arithmetic and Memories

    1. Ioannis Kouretas, Vassilis Paliouras
      Pages 93-102
    2. Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Lars Lundheim, Asghar Havashki
      Pages 103-115
    3. Florian Bauer, Georg Georgakos, Doris Schmitt-Landsiedel
      Pages 116-125
    4. Yan Li, Helmut Schneider, Florian Schnabel, Roland Thewes, Doris Schmitt-Landsiedel
      Pages 126-135
  5. Session 4: Variability and Statistical Timing

    1. Massimo Alioto, Gaetano Palumbo, Melita Pennisi
      Pages 136-145
    2. Monica Figueiredo, Rui L. Aguiar
      Pages 146-155
    3. Bing Li, Christoph Knoth, Walter Schneider, Manuel Schmidt, Ulf Schlichtmann
      Pages 156-166
    4. Walter Schneider, Manuel Schmidt, Bing Li, Ulf Schlichtmann
      Pages 167-177
    5. Howard Chen, Scott Neely, Jinjun Xiong, Vladimir Zolotov, Chandu Visweswariah
      Pages 178-187
  6. Session 5: Synchronization and Interconnect

    1. Francisco Fernández-Nogueira, Josep Carmona
      Pages 188-198

About these proceedings

Introduction

This book constitutes the thoroughly refereed post-conference proceedings of 18th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2008, featuring Integrated Circuit and System Design, held in Lisbon, Portugal during September 10-12, 2008.

The 31 revised full papers and 10 revised poster papers presented together with 3 invited talks and 4 papers from a special session on reconfigurable architectures were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on low-leakage and subthreshold circuits, low-power methods and models, arithmetic and memories, variability and statistical timing, synchronization and interconnect, power supplies and switching noise, low-power circuits; reconfigurable architectures, circuits and methods, power and delay modeling, as well as power optimizations addressing reconfigurable architectures.

Keywords

CMOS DSP Filter FinFET active-mode leakage circuit analysis circuit design circuit optimization coloured petri net cryptography embedded system energy optimization energy saving field-effect transistor integrated circuit

Editors and affiliations

  • Lars Svensson
    • 1
  • José Monteiro
    • 2
  1. 1.Department of Computer EngineeringChalmers University of TechnologyGöteborgSweden
  2. 2.INESC-IDLisbonPortugal

Bibliographic information

  • DOI https://doi.org/10.1007/978-3-540-95948-9
  • Copyright Information Springer-Verlag Berlin Heidelberg 2009
  • Publisher Name Springer, Berlin, Heidelberg
  • eBook Packages Computer Science
  • Print ISBN 978-3-540-95947-2
  • Online ISBN 978-3-540-95948-9
  • Series Print ISSN 0302-9743
  • Series Online ISSN 1611-3349
  • About this book