High Performance Embedded Architectures and Compilers

Fourth International Conference, HiPEAC 2009, Paphos, Cyprus, January 25-28, 2009. Proceedings

  • André Seznec
  • Joel Emer
  • Michael O’Boyle
  • Margaret Martonosi
  • Theo Ungerer
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5409)

Table of contents

  1. Front Matter
  2. Invited Program

  3. I Dynamic Translation and Optimisation

    1. Mohammad Ansari, Mikel Luján, Christos Kotselidis, Kim Jarvis, Chris Kirkham, Ian Watson
      Pages 4-18
    2. Víctor J. Jiménez, Lluís Vilanova, Isaac Gelado, Marisa Gil, Grigori Fursin, Nacho Navarro
      Pages 19-33
    3. Grigori Fursin, Olivier Temam
      Pages 34-49
  4. II Low Level Scheduling

    1. Mattias V. Eriksson, Christoph W. Kessler
      Pages 65-79
    2. Mohammed Fellahi, Albert Cohen
      Pages 80-94
    3. Martin Thuresson, Magnus Själander, Per Stenstrom
      Pages 95-109
  5. III Parallelism and Resource Control

    1. Kenzo Van Craeynest, Stijn Eyerman, Lieven Eeckhout
      Pages 110-124
    2. Jörg Mische, Sascha Uhrig, Florian Kluge, Theo Ungerer
      Pages 125-139
    3. Ghiath Al-Kadi, Andrei Sergeevich Terechko
      Pages 140-152
    4. Frederik Vandeputte, Lieven Eeckhout
      Pages 153-167
  6. IV Communication

    1. Lee W. Howes, Anton Lokhmotov, Alastair F. Donaldson, Paul H. J. Kelly
      Pages 168-182
    2. Theo Kluter, Philip Brisk, Edoardo Charbon, Paolo Ienne
      Pages 183-197
    3. Sai Prashanth Muralidhara, Mahmut Kandemir
      Pages 198-215
  7. V Mapping for CMPs

    1. Maik Nijhuis, Herbert Bos, Henri E. Bal, Cédric Augonnet
      Pages 216-230
    2. Yang Ding, Mahmut Kandemir, Mary Jane Irwin, Padma Raghavan
      Pages 231-247
    3. Major Bhadauria, Vince Weaver, Sally A. McKee
      Pages 248-262

About these proceedings

Introduction

This book constitutes the refereed proceedings of the Fourth International Conference on High Performance Embedded Architectures and Compilers, HiPEAC 2009, held in Paphos, Cyprus, in January  2009.

The 27 revised full papers presented together with 2 invited keynote paper were carefully reviewed and selected from 97 submissions. The papers are organized in topical sections on dynamic translation and optimisation, low level scheduling, parallelism and resource control, communication, mapping for CMPs, power, cache issues as well as parallel embedded applications.

Keywords

Ada Cluster H.264 Multithreading Processing Scheduling Scheme code compression exascale computing heterogenous architectures hyperthreading manycore memory performance mul optimization

Editors and affiliations

  • André Seznec
    • 1
  • Joel Emer
    • 2
  • Michael O’Boyle
    • 3
  • Margaret Martonosi
    • 4
  • Theo Ungerer
    • 5
  1. 1.IRISA, Campus de BeaulieuRennes CedexFrance
  2. 2.Intel CorporationMassachusetts Microprocessor Design CenterHudsonUSA
  3. 3.School of InformaticsInstitute for Computing Systems ArchitectureEdinburghUnited Kingdom
  4. 4.Department of Electrical EngineeringPrinceton UniversityPrincetonUSA
  5. 5.Department of Computer ScienceUniversity of AugsburgAugsburgGermany

Bibliographic information

  • DOI https://doi.org/10.1007/978-3-540-92990-1
  • Copyright Information Springer-Verlag Berlin Heidelberg 2009
  • Publisher Name Springer, Berlin, Heidelberg
  • eBook Packages Computer Science
  • Print ISBN 978-3-540-92989-5
  • Online ISBN 978-3-540-92990-1
  • Series Print ISSN 0302-9743
  • Series Online ISSN 1611-3349
  • About this book