High Performance Embedded Architectures and Compilers

Third International Conference, HiPEAC 2008, Göteborg, Sweden, January 27-29, 2008. Proceedings

  • Editors
  • Per Stenström
  • Michel Dubois
  • Manolis Katevenis
  • Rajiv Gupta
  • Theo Ungerer
Conference proceedings HiPEAC 2008

Part of the Lecture Notes in Computer Science book series (LNCS, volume 4917)

Table of contents

  1. Front Matter
  2. Invited Program

    1. Front Matter
      Pages 1-1
  3. I Multithreaded and Multicore Processors

    1. Front Matter
      Pages 7-7
    2. Filip Blagojevic, Xizhou Feng, Kirk W. Cameron, Dimitrios S. Nikolopoulos
      Pages 38-52
  4. IIa Reconfigurable - ASIP

    1. Front Matter
      Pages 53-53
    2. Ricardo Chaves, Blagomir Donchev, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis
      Pages 55-65
    3. Frank Bouwens, Mladen Berekovic, Bjorn De Sutter, Georgi Gaydadjiev
      Pages 66-81
    4. Jochem Govers, Jos Huisken, Mladen Berekovic, Olivier Rousseaux, Frank Bouwens, Michael de Nil et al.
      Pages 82-96
  5. IIb Compiler Optimizations

    1. Front Matter
      Pages 97-97
    2. Tzi-cker Chiueh
      Pages 99-113
    3. Stijn Eyerman, Lieven Eeckhout, James E. Smith
      Pages 114-129
    4. Marco Cornero, Roberto Costa, Ricardo Fernández Pascual, Andrea C. Ornstein, Erven Rohou
      Pages 130-144
  6. III Industrial Processors and Application Parallelization

    1. Front Matter
      Pages 145-145
    2. Todd T. Hahn, Eric Stotzer, Dineel Sule, Mike Asal
      Pages 147-160
    3. Hans Vandierendonck, Sean Rul, Michiel Questier, Koen De Bosschere
      Pages 161-175
    4. Harald Servat, Cecilia González-Alvarez, Xavier Aguilar, Daniel Cabrera-Benitez, Daniel Jiménez-González
      Pages 176-190
  7. IV Power-Aware Techniques

    1. Front Matter
      Pages 191-191

About these proceedings

Keywords

Compiler Random Access Memory Variable algorithms compiler techniques complexity computer architecture dataflow programming dynamic compilation embedded systems extensible processors high-performance architecture memory system optimization network computing processor

Bibliographic information

  • DOI https://doi.org/10.1007/978-3-540-77560-7
  • Copyright Information Springer-Verlag Berlin Heidelberg 2008
  • Publisher Name Springer, Berlin, Heidelberg
  • eBook Packages Computer Science
  • Print ISBN 978-3-540-77559-1
  • Online ISBN 978-3-540-77560-7
  • Series Print ISSN 0302-9743
  • Series Online ISSN 1611-3349
  • About this book