Transactions on High-Performance Embedded Architectures and Compilers I

  • Per Stenström

Part of the Lecture Notes in Computer Science book series (LNCS, volume 4050)

Table of contents

  1. Front Matter
  2. High Performance Processor Chips

    1. Maurice V. Wilkes
      Pages 1-4
    2. Koen De Bosschere, Wayne Luk, Xavier Martorell, Nacho Navarro, Mike O’Boyle, Dionisios Pnevmatikatos et al.
      Pages 5-29
  3. Part 1: First International Conference on High-Performance Embedded Architectures and Compilers, HiPEAC 2005. Best Papers

    1. Front Matter
      Pages 31-31
    2. Per Stenström
      Pages 33-33
    3. Grigori Fursin, Albert Cohen, Michael O’Boyle, Olivier Temam
      Pages 34-53
    4. Michael J. Geiger, Sally A. McKee, Gary S. Tyson
      Pages 54-73
    5. Dries Buytaert, Kris Venstermans, Lieven Eeckhout, Koen De Bosschere
      Pages 74-94
    6. Weidong Shi, Chenghuai Lu, Hsien-Hsin S. Lee
      Pages 95-115
  4. Part 2: Optimizing Compilers

    1. Front Matter
      Pages 137-137
    2. Mike O’Boyle, François Bodin, Marcelo Cintra
      Pages 139-139
    3. Nicholas Nethercote, Doug Burger, Kathryn S. McKinley
      Pages 140-158
    4. Harald Devos, Kristof Beyls, Mark Christiaens, Jan Van Campenhout, Erik H. D’Hollander, Dirk Stroobandt
      Pages 159-178
    5. Fakhreddine Ghaffari, Michel Auguin, Mohamed Abid, Maher Ben Jemaa
      Pages 179-193
    6. Shane Ryoo, Sain-Zee Ueng, Christopher I. Rodrigues, Robert E. Kidd, Matthew I. Frank, Wen-mei W. Hwu
      Pages 194-213
  5. Part 3: ACM International Conference on Computing Frontiers 2006. Best Papers

    1. Front Matter
      Pages 235-235
    2. Sally A. McKee
      Pages 237-238
    3. Iyad Al Khatib, Davide Bertozzi, Francesco Poletti, Luca Benini, Axel Jantsch, Mohamed Bechara et al.
      Pages 239-258

About these proceedings

Keywords

Compiler Computer Hardware Monitor algorithms calculus compiler techniques computer architecture embedded systems high-performance architecture memory system optimization network computing on-chip multiprocessors parallel architectures processor

Editors and affiliations

  • Per Stenström
    • 1
  1. 1.Department of Computer Science and EngineeringChalmers University of TechnologyGothenburgSweden

Bibliographic information

  • DOI https://doi.org/10.1007/978-3-540-71528-3
  • Copyright Information Springer-Verlag Berlin Heidelberg 2007
  • Publisher Name Springer, Berlin, Heidelberg
  • eBook Packages Computer Science
  • Print ISBN 978-3-540-71527-6
  • Online ISBN 978-3-540-71528-3
  • Series Print ISSN 0302-9743
  • Series Online ISSN 1611-3349
  • About this book