About this book
This book addresses the need for energy-efficient amplifiers, providing gain enhancement strategies, suitable to run in parallel with lower supply voltages, by introducing a new family of single-stage cascode-free amplifiers, with proper design, optimization, fabrication and experimental evaluation. The authors describe several topologies, using the UMC 130 nm CMOS technology node with standard-VT devices, for proof-of-concept, achieving results far beyond what is achievable with a classic single-stage folded-cascode amplifier. Readers will learn about a new family of circuits with a broad range of applications, together with the familiarization with a state-of-the-art electronic design automation methodology used to explore the design space of the proposed circuit family.
- Introduces a new family of CMOS cascode-free amplifiers with high energy-efficiency and improved gain;
- Describes innovative circuit topologies: the Voltage-Combiners biased OTA (supplied by a 3.3 V source); the Voltage-Combiners biased OTA with Current Starving, for higher gain and energy-efficiency (supplied by a 3.3 V source); the Folded Voltage-Combiners biased OTA (supplied by sources from 1.2 V to 0.9 V); and a Dynamic Voltage-Combiners biased OTA, for high performance analog-to-digital converters (supplied by a 1.2 V source);
- Enables readers to reach better results than what is achievable with classic single-stage folded-cascode amplifiers, with state-of-the-art results in the context of dynamically biased amplifiers;
Analog Amplifier Voltage-Combiners Dynamic, Switched-Capacitors Gain Enhancement Evolutionary Computation