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Thread and Data Mapping for Multicore Systems

Improving Communication and Memory Accesses

  • Eduardo H. M. Cruz
  • Matthias Diener
  • Philippe O. A. Navaux
Book

Part of the SpringerBriefs in Computer Science book series (BRIEFSCOMPUTER)

Table of contents

  1. Front Matter
    Pages i-ix
  2. Eduardo H. M. Cruz, Matthias Diener, Philippe O. A. Navaux
    Pages 1-8
  3. Eduardo H. M. Cruz, Matthias Diener, Philippe O. A. Navaux
    Pages 9-17
  4. Eduardo H. M. Cruz, Matthias Diener, Philippe O. A. Navaux
    Pages 19-34
  5. Eduardo H. M. Cruz, Matthias Diener, Philippe O. A. Navaux
    Pages 35-48
  6. Eduardo H. M. Cruz, Matthias Diener, Philippe O. A. Navaux
    Pages 49-49
  7. Back Matter
    Pages 51-54

About this book

Introduction

This book presents a study on how thread and data mapping techniques can be used to improve the  performance of multi-core architectures.

It describes how the memory hierarchy introduces non-uniform memory access, and how mapping can be used to reduce the memory access latency in current hardware architectures.

On the software side, this book describes the characteristics present in parallel applications that are used by mapping techniques to improve memory access.

Several state-of-the-art methods are analyzed, and the benefits and drawbacks of each one are identified.

Keywords

Data Movement Thread Mapping Cache Memory Non-uniform memory access Data Mapping

Authors and affiliations

  • Eduardo H. M. Cruz
    • 1
  • Matthias Diener
    • 2
  • Philippe O. A. Navaux
    • 3
  1. 1.Federal Institute of Parana (IFPR)Paranavai, ParanaBrazil
  2. 2.University of Illinois at Urbana-ChampaignUrbanaUSA
  3. 3.Informatics InstituteFederal University of Rio Grande do Sul (UFRGS)Porto AlegreBrazil

Bibliographic information

  • DOI https://doi.org/10.1007/978-3-319-91074-1
  • Copyright Information The Author(s), under exclusive licence to Springer International Publishing AG, part of Springer Nature 2018
  • Publisher Name Springer, Cham
  • eBook Packages Computer Science Computer Science (R0)
  • Print ISBN 978-3-319-91073-4
  • Online ISBN 978-3-319-91074-1
  • Series Print ISSN 2191-5768
  • Series Online ISSN 2191-5776
  • Buy this book on publisher's site