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© 2018

Logic Synthesis for Finite State Machines Based on Linear Chains of States

Foundations, Recent Developments and Challenges

Book

Part of the Studies in Systems, Decision and Control book series (SSDC, volume 113)

Table of contents

  1. Front Matter
    Pages i-viii
  2. Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski
    Pages 1-5
  3. Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski
    Pages 7-34
  4. Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski
    Pages 35-65
  5. Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski
    Pages 67-93
  6. Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski
    Pages 95-119
  7. Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski
    Pages 121-153
  8. Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski
    Pages 155-186
  9. Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski
    Pages 187-220
  10. Back Matter
    Pages 221-225

About this book

Introduction

This book discusses Moore finite state machines (FSMs) implemented with field programmable gate arrays (FPGAs) including look-up table (LUT) elements and embedded memory blocks (EMBs). To minimize the number of LUTs in FSM logic circuits, the authors propose replacing a state register with a state counter. They also put forward an approach allowing linear chains of states to be created, which simplifies the system of input memory functions and, therefore, decreases the number of LUTs in the resulting FSM circuit. The authors combine this approach with using EMBs to implement the system of output functions (microoperations). This allows a significant decrease in the number of LUTs, as well as eliminating a lot of interconnections in the FSM logic circuit. As a rule, it also reduces the area occupied by the circuit and diminishes the resulting power dissipation.

This book is an interesting and valuable resource for students and postgraduates in the area of computer science, as well as for designers of digital systems that included complex control units


Keywords

Linear Chains of States Finite State Machine Logic Synthesis Field-Programmable Gate Arrays Look-up Table Element Embedded Memory Block

Authors and affiliations

  1. 1.Institute of Metrology, Electronics and Computer ScienceUniversity of Zielona GóraZielona GóraPoland
  2. 2.Institute of Metrology, Electronics and Computer ScienceUniversity of Zielona GóraZielona GóraPoland
  3. 3.Institute of Metrology, Electronics and Computer ScienceUniversity of Zielona GóraZielona GóraPoland

Bibliographic information

  • Book Title Logic Synthesis for Finite State Machines Based on Linear Chains of States
  • Book Subtitle Foundations, Recent Developments and Challenges
  • Authors Alexander Barkalov
    Larysa Titarenko
    Jacek Bieganowski
  • Series Title Studies in Systems, Decision and Control
  • Series Abbreviated Title Studies in Systems, Decision and Control
  • DOI https://doi.org/10.1007/978-3-319-59837-6
  • Copyright Information Springer International Publishing AG 2018
  • Publisher Name Springer, Cham
  • eBook Packages Engineering Engineering (R0)
  • Hardcover ISBN 978-3-319-59836-9
  • Softcover ISBN 978-3-319-86714-4
  • eBook ISBN 978-3-319-59837-6
  • Series ISSN 2198-4182
  • Series E-ISSN 2198-4190
  • Edition Number 1
  • Number of Pages VIII, 225
  • Number of Illustrations 145 b/w illustrations, 0 illustrations in colour
  • Topics Computational Intelligence
    Circuits and Systems
  • Buy this book on publisher's site