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Logic Synthesis for FPGA-Based Finite State Machines

  • Alexander Barkalov
  • Larysa Titarenko
  • Malgorzata Kolopienczyk
  • Kamil Mielcarek
  • Grzegorz Bazydlo

Part of the Studies in Systems, Decision and Control book series (SSDC, volume 38)

Table of contents

  1. Front Matter
    Pages i-xiv
  2. Alexander Barkalov, Larysa Titarenko, Malgorzata Kolopienczyk, Kamil Mielcarek, Grzegorz Bazydlo
    Pages 1-31
  3. Alexander Barkalov, Larysa Titarenko, Malgorzata Kolopienczyk, Kamil Mielcarek, Grzegorz Bazydlo
    Pages 33-64
  4. Alexander Barkalov, Larysa Titarenko, Malgorzata Kolopienczyk, Kamil Mielcarek, Grzegorz Bazydlo
    Pages 65-95
  5. Alexander Barkalov, Larysa Titarenko, Malgorzata Kolopienczyk, Kamil Mielcarek, Grzegorz Bazydlo
    Pages 97-127
  6. Alexander Barkalov, Larysa Titarenko, Malgorzata Kolopienczyk, Kamil Mielcarek, Grzegorz Bazydlo
    Pages 129-159
  7. Alexander Barkalov, Larysa Titarenko, Malgorzata Kolopienczyk, Kamil Mielcarek, Grzegorz Bazydlo
    Pages 161-191
  8. Alexander Barkalov, Larysa Titarenko, Malgorzata Kolopienczyk, Kamil Mielcarek, Grzegorz Bazydlo
    Pages 193-237
  9. Alexander Barkalov, Larysa Titarenko, Malgorzata Kolopienczyk, Kamil Mielcarek, Grzegorz Bazydlo
    Pages 239-276
  10. Back Matter
    Pages 277-280

About this book

Introduction

This book discusses control units represented by the model of a finite state machine (FSM). It contains various original methods and takes into account the peculiarities of field-programmable gate arrays (FPGA) chips and a FSM model. It shows that one of the peculiarities of FPGA chips is the existence of embedded memory blocks (EMB). The book is devoted to the solution of problems of logic synthesis and reduction of hardware amount in control units. The book will be interesting and useful for researchers and PhD students in the area of Electrical Engineering and Computer Science, as well as for designers of modern digital systems.

Keywords

Embedded Memory Block Field-programmable Gate Arrays Finite State Machine Graph-scheme of Algorithms Logic Synthesis Look-up Table Element Structural Decomposition

Authors and affiliations

  • Alexander Barkalov
    • 1
  • Larysa Titarenko
    • 2
  • Malgorzata Kolopienczyk
    • 3
  • Kamil Mielcarek
    • 4
  • Grzegorz Bazydlo
    • 5
  1. 1.University of Zielona Gora Institute of Informatics and ElectrZielona GoraPoland
  2. 2.University of Zielona Gora Inst Informatics & ElectronicsZielona GoraPoland
  3. 3.Institute of Informatics and ElectronicsUniversity of Zielona GóraZielona GóraPoland
  4. 4.Institute of Informatics and ElectronicsUniversity of Zielona GóraZielona GóraPoland
  5. 5.Institute of Informatics and ElectronicsUniversity of Zielona GóraZielona GóraPoland

Bibliographic information

  • DOI https://doi.org/10.1007/978-3-319-24202-6
  • Copyright Information Springer International Publishing Switzerland 2016
  • Publisher Name Springer, Cham
  • eBook Packages Engineering
  • Print ISBN 978-3-319-24200-2
  • Online ISBN 978-3-319-24202-6
  • Series Print ISSN 2198-4182
  • Series Online ISSN 2198-4190
  • Buy this book on publisher's site