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Timing Channels in Cryptography

A Micro-Architectural Perspective

  • Chester Rebeiro
  • Debdeep Mukhopadhyay
  • Sarani Bhattacharya

Table of contents

  1. Front Matter
    Pages i-xvii
  2. Chester Rebeiro, Debdeep Mukhopadhyay, Sarani Bhattacharya
    Pages 1-11
  3. Chester Rebeiro, Debdeep Mukhopadhyay, Sarani Bhattacharya
    Pages 13-35
  4. Chester Rebeiro, Debdeep Mukhopadhyay, Sarani Bhattacharya
    Pages 37-51
  5. Chester Rebeiro, Debdeep Mukhopadhyay, Sarani Bhattacharya
    Pages 53-70
  6. Chester Rebeiro, Debdeep Mukhopadhyay, Sarani Bhattacharya
    Pages 71-80
  7. Chester Rebeiro, Debdeep Mukhopadhyay, Sarani Bhattacharya
    Pages 81-94
  8. Chester Rebeiro, Debdeep Mukhopadhyay, Sarani Bhattacharya
    Pages 95-108
  9. Chester Rebeiro, Debdeep Mukhopadhyay, Sarani Bhattacharya
    Pages 109-124
  10. Chester Rebeiro, Debdeep Mukhopadhyay, Sarani Bhattacharya
    Pages 125-137
  11. Chester Rebeiro, Debdeep Mukhopadhyay, Sarani Bhattacharya
    Pages 139-149
  12. Back Matter
    Pages 151-152

About this book

Introduction

This book deals with timing attacks on software implementations of encryption algorithms. It describes and analyzes various unintended covert timing channels that are formed when ciphers are executed in microprocessors. Modern superscalar microprocessors are considered, which are enabled with features such as multi-threaded, pipelined, parallel, speculative, and out-of-order execution. Various timing attack algorithms are described and analyzed for  block ciphers as well as public-key ciphers. The interplay between the cipher implementation, system architecture, and the attack's success is analyzed. Further hardware and software countermeasures are discussed with the aim of illustrating methods to build systems that can protect against these attacks.

  • Discusses various timing attack algorithms in detail allowing readers to reconstruct the attack.
  • Provides several experimental results to support the theoretical analysis provided in the book.
  • Analyzes information leakage from cache memories and branch prediction units in the processor.
  • Examines information leakage models that would help quantify leakage in a covert timing channels.

Keywords

Branch Prediction Attacks Cache Attacks Hardware Security Micro-architecture Attacks Timing Attacks

Authors and affiliations

  • Chester Rebeiro
    • 1
  • Debdeep Mukhopadhyay
    • 2
  • Sarani Bhattacharya
    • 3
  1. 1.Columbia UniversityStamfordUSA
  2. 2.Indian Institute of TechnologyKharagpurIndia
  3. 3.Department of Computer Science and EnginIIT KharagpurKharagpurIndia

Bibliographic information

  • DOI https://doi.org/10.1007/978-3-319-12370-7
  • Copyright Information Springer International Publishing Switzerland 2015
  • Publisher Name Springer, Cham
  • eBook Packages Engineering
  • Print ISBN 978-3-319-12369-1
  • Online ISBN 978-3-319-12370-7
  • Buy this book on publisher's site