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Logic Synthesis for FPGA-Based Control Units

Structural Decomposition in Logic Design

  • Alexander Barkalov
  • Larysa Titarenko
  • Kamil Mielcarek
  • Sławomir Chmielewski
Book

Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 636)

Table of contents

  1. Front Matter
    Pages i-xvi
  2. Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Sławomir Chmielewski
    Pages 1-22
  3. Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Sławomir Chmielewski
    Pages 23-59
  4. Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Sławomir Chmielewski
    Pages 61-90
  5. Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Sławomir Chmielewski
    Pages 91-116
  6. Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Sławomir Chmielewski
    Pages 117-149
  7. Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Sławomir Chmielewski
    Pages 151-179
  8. Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Sławomir Chmielewski
    Pages 181-212
  9. Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Sławomir Chmielewski
    Pages 213-241
  10. Back Matter
    Pages 243-247

About this book

Introduction

This book focuses on control units, which are a vital part of modern digital systems, and responsible for the efficiency of controlled systems. The model of a finite state machine (FSM) is often used to represent the behavior of a control unit. As a rule, control units have irregular structures that make it impossible to design their logic circuits using the standard library cells. Design methods depend strongly on such factors as the FSM used, specific features of the logic elements implemented in the FSM logic circuit, and the characteristics of the control algorithm to be interpreted.

This book discusses Moore and Mealy FSMs implemented with FPGA chips, including look-up table elements (LUT) and embedded memory blocks (EMB). It is crucial to minimize the number of LUTs and EMBs in an FSM logic circuit, as well as to make the interconnections between the logic elements more regular, and various methods of structural decompositions can be used to solve this problem. These methods are reduced to the presentation of an FSM circuit as a composition of different logic blocks, the majority of which implement systems of intermediate logic functions different (and much simpler) than input memory functions and FSM output functions. The structural decomposition results in multilevel FSM circuits having fewer logic elements than equivalent single-level circuits. The book describes well-known methods of structural decomposition and proposes new ones, examining their impact on the final amount of hardware in an FSM circuit. It is of interest to students and postgraduates in the area of Computer Science, as well as experts involved in designing digital systems with complex control units. The proposed models and design methods open new possibilities for creating logic circuits of control units with an optimal amount of hardware and regular interconnections.

 


Keywords

Finite State Machine Logic Synthesis Field-Programmable Gate Arrays FPGA Look-up Table Element Embedded Memory Block Graph-Scheme of Algorithms Structural Decomposition

Authors and affiliations

  • Alexander Barkalov
    • 1
  • Larysa Titarenko
    • 2
  • Kamil Mielcarek
    • 3
  • Sławomir Chmielewski
    • 4
  1. 1.Institute of Metrology, Electronics and Computer ScienceUniversity of Zielona GóraZielona GóraPoland
  2. 2.Institute of Metrology, Electronics and Computer ScienceUniversity of Zielona GóraZielona GóraPoland
  3. 3.Institute of Metrology, Electronics and Computer ScienceUniversity of Zielona GóraZielona GóraPoland
  4. 4.Institute of Science and Technology Automatics and Robotics, MetallurgyState Higher Vocational School (PWSZ)GłogówPoland

Bibliographic information