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© 2020

Deep In-memory Architectures for Machine Learning

Book

Table of contents

  1. Front Matter
    Pages i-x
  2. Mingu Kang, Sujan Gonugondla, Naresh R. Shanbhag
    Pages 1-6
  3. Mingu Kang, Sujan Gonugondla, Naresh R. Shanbhag
    Pages 7-47
  4. Mingu Kang, Sujan Gonugondla, Naresh R. Shanbhag
    Pages 49-79
  5. Mingu Kang, Sujan Gonugondla, Naresh R. Shanbhag
    Pages 81-100
  6. Mingu Kang, Sujan Gonugondla, Naresh R. Shanbhag
    Pages 101-137
  7. Mingu Kang, Sujan Gonugondla, Naresh R. Shanbhag
    Pages 139-160
  8. Mingu Kang, Sujan Gonugondla, Naresh R. Shanbhag
    Pages 161-162
  9. Mingu Kang, Sujan Gonugondla, Naresh R. Shanbhag
    Pages C1-C1
  10. Back Matter
    Pages 163-174

About this book

Introduction

This book describes the recent innovation of deep in-memory architectures for realizing AI systems that operate at the edge of energy-latency-accuracy trade-offs. From first principles to lab prototypes, this book provides a comprehensive view of this emerging topic for both the practicing engineer in industry and the researcher in academia. The book is a journey into the exciting world of AI systems in hardware.


  • Describes deep in-memory architectures for AI systems from first principles, covering both circuit design and architectures;
  • Discusses how DIMAs pushes the limits of energy-delay product of decision-making machines via its intrinsic energy-SNR trade-off;
  • Offers readers a unique Shannon-inspired perspective to understand the system-level energy-accuracy trade-off and robustness in such architectures;
  • Illustrates principles and design methods via case studies of actual integrated circuit prototypes with measured results in the laboratory;
  • Presents DIMA's various models to evaluate DIMA's decision-making accuracy, energy, and latency trade-offs with various design parameter.

Keywords

machine learning in hardware analog in-memory architectures Deep In-memory Architecture Shannon-inspired architecture energy-latency-accuracy trade-offs in AI

Authors and affiliations

  1. 1.IBM Thomas J. Watson Research CenterYorktown HeightsUSA
  2. 2.University of Illinois at Urbana-ChampaignUrbanaUSA
  3. 3.University of Illinois at Urbana-ChampaignUrbanaUSA

About the authors

Mingu Kang received the B.S. and M.S. degrees in Electrical and Electronic Engineering from Yonsei University, Seoul, South Korea, in 2007 and 2009, respectively, and the Ph.D. degree in Electrical and Computer Engineering from the University of Illinois at Urbana–Champaign, Champaign, IL, USA, in 2017. From 2009 to 2012, he was with the Memory Division, Samsung Electronics, Hwaseong, South Korea, where he was involved in the circuit and architecture design of phase change memory (PRAM). Since 2017, he has been with the IBM Thomas J. Watson Research Center, Yorktown Heights, NY, USA, where he designs machine learning accelerator architectures. His current research interests include low-power integrated circuits, architectures, and systems for machine learning, signal processing, and neuromorphic computing.

 

Sujan Gonugondla received the B.Tech and M.Tech. degrees in Electrical Engineering from the Indian Institute of Technology Madras, Chennai, India, in 2014. He is currently pursuing the Ph.D. degree in the Department of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign, Champaign, IL, USA. His current research interests include low-power integrated circuits specifically algorithm hardware co-design for machine learning systems on resource constrained environments. Sujan

Gonugondla is a recipient of the Dr. Ok Kyun Kim Fellowship 2018-19 from the ECE department at the University of Illinois at Urbana-Champaign and the ADI Outstanding Student Designer Award 2018.

 

Naresh R. Shanbhag is the Jack Kilby Professor of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. He received his Ph.D. degree from the University of Minnesota (1993) in Electrical Engineering. From 1993 to 1995, he worked at AT&T Bell Laboratories at Murray Hill where he led the design of high-speed transceiver chip-sets for very high-speed digital subscriber line (VDSL), before joining the University of Illinois at Urbana- Champaign in August 1995. He has held visiting faculty appointments at the National Taiwan University (Aug.-Dec. 2007) and Stanford University (Aug.-Dec. 2014). His research interests are in the design of energy-efficient integrated circuits and systems for communications, signal processing and machine learning. He has more than 200 publications in this area and holds thirteen US patents. Dr. Shanbhag received the 2018 SIA/SRC University Research Award, became an IEEE Fellow in 2006, received the 2010 Richard Newton GSRC Industrial Impact Award, the IEEE Circuits and Systems Society Distinguished Lecturership in 1997, the National Science Foundation CAREER Award in 1996, and multiple best paper awards. In 2000, Dr. Shanbhag co-founded and served as the Chief Technology Officer of Intersymbol Communications, Inc., (acquired in 2007 by Finisar Corporation) a semiconductor start-up that provided DSP-enhanced mixed-signal ICs for electronic dispersion compensation of OC-192 optical links. From 2013-17, he was the founding Director of the Systems On Nanoscale Information fabriCs (SONIC) Center, a 5-year multi- university center funded by DARPA and SRC under the STARnet program.

Bibliographic information