Defect and Fault Tolerance in VLSI Systems

Volume 2

  • C. H. Stapper
  • V. K. Jain
  • G. Saucier

Table of contents

  1. Front Matter
    Pages i-xiii
  2. Models for VLSI Manufacturing Yield

  3. Models for Defects and Yield

    1. J. Pineda de Gyvez, J. A. G. Jess
      Pages 47-61
    2. A. V. Ferris-Prabhu, M. A. Retersdorf
      Pages 63-73
  4. Implementation of Wafer Scale Integration

  5. Fault Tolerance

  6. Array Processors

  7. New Approaches and Issues

    1. J. Mauer, D. Seeger, R. DellaGuardia
      Pages 209-218
    2. K. Kubiak, W. K. Fuchs
      Pages 219-226
    3. A. G. Andreou, S. A. Kontogiorgis
      Pages 227-240
  8. Yield and Manufacturing Defects

  9. Designs for Wafer Scale Integration

    1. H. Ito, N. Suzuki
      Pages 283-294
    2. J. G. Delgado-Frias, W. R. Moore
      Pages 305-313
  10. Back Matter
    Pages 315-316

About this book


Higher circuit densities, increasingly more complex application ohjectives, and advanced packaging technologies have suhstantially increased the need to incorporate defect-tolerance and fault-tolerance in the design of VLSI and WSI systems. The goals of defect-tolerance and fault-tolerance are yield enhancement and improved reliahility. The emphasis on this area has resulted in a new field of interdisciplinary scientific research. I n fact, advanced methods of defect/fault control and tolerance are resulting in enhanced manufacturahility and productivity of integrated circuit chips, VI.SI systems, and wafer scale integrated circuits. In 1987, Dr. W. Moore organized an "International Workshop on Designing for Yield" at Oxford University. Edited papers of that workshop were published in reference [II. The participants in that workshop agreed that meetings of this type should he con­ tinued. preferahly on a yearly hasis. It was Dr. I. Koren who organized the "IEEE Inter national Workshop on Defect and Fault Tolerance in VLSI Systems" in Springfield Massachusetts the next year. Selected papers from that workshop were puhlished as the first volume of this series [21.


RAM SRAM VLSI communication integrated circuit logic programming

Editors and affiliations

  • C. H. Stapper
    • 1
  • V. K. Jain
    • 2
  • G. Saucier
    • 3
  1. 1.IBMEssex JunctionUSA
  2. 2.University of South FloridaTampaUSA
  3. 3.Institute National Polytechnique de Grenoble/CSIGrenobleFrance

Bibliographic information