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© 1997

Reasoning in Boolean Networks

Logic Synthesis and Verification using Testing Techniques

Book

Part of the Frontiers in Electronic Testing book series (FRET, volume 9)

Table of contents

  1. Front Matter
    Pages i-xv
  2. Wolfgang Kunz, Dominik Stoffel
    Pages 1-15
  3. Wolfgang Kunz, Dominik Stoffel
    Pages 17-47
  4. Wolfgang Kunz, Dominik Stoffel
    Pages 49-73
  5. Wolfgang Kunz, Dominik Stoffel
    Pages 75-99
  6. Wolfgang Kunz, Dominik Stoffel
    Pages 101-161
  7. Wolfgang Kunz, Dominik Stoffel
    Pages 163-195
  8. Wolfgang Kunz, Dominik Stoffel
    Pages 197-199
  9. Back Matter
    Pages 201-230

About this book

Introduction

Reasoning in Boolean Networks provides a detailed treatment of recent research advances in algorithmic techniques for logic synthesis, test generation and formal verification of digital circuits. The book presents the central idea of approaching design automation problems for logic-level circuits by specific Boolean reasoning techniques.
While Boolean reasoning techniques have been a central element of two-level circuit theory for many decades Reasoning in Boolean Networks describes a basic reasoning methodology for multi-level circuits. This leads to a unified view on two-level and multi-level logic synthesis. The presented reasoning techniques are applied to various CAD-problems to demonstrate their usefulness for today's industrially relevant problems.
Reasoning in Boolean Networks provides lucid descriptions of basic algorithmic concepts in automatic test pattern generation, logic synthesis and verification and elaborates their intimate relationship to provide further intuition and insight into the subject. Numerous examples are provide for ease in understanding the material.
Reasoning in Boolean Networks is intended for researchers in logic synthesis, VLSI testing and formal verification as well as for integrated circuit designers who want to enhance their understanding of basic CAD methodologies.

Keywords

VLSI algorithms automation circuit circuit design computer-aided design (CAD) formal verification integrated circuit logic material network networks optimization verification

Authors and affiliations

  1. 1.University of PotsdamGermany

Bibliographic information

  • Book Title Reasoning in Boolean Networks
  • Book Subtitle Logic Synthesis and Verification using Testing Techniques
  • Authors Wolfgang Kunz
    Dominik Stoffel
  • Series Title Frontiers in Electronic Testing
  • DOI https://doi.org/10.1007/978-1-4757-2572-8
  • Copyright Information Springer-Verlag US 1997
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Hardcover ISBN 978-0-7923-9921-6
  • Softcover ISBN 978-1-4419-5176-2
  • eBook ISBN 978-1-4757-2572-8
  • Series ISSN 0929-1296
  • Edition Number 1
  • Number of Pages XVI, 230
  • Number of Illustrations 0 b/w illustrations, 0 illustrations in colour
  • Topics Computer-Aided Engineering (CAD, CAE) and Design
    Electrical Engineering
  • Buy this book on publisher's site