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High Level Synthesis of ASICs under Timing and Synchronization Constraints

  • David C. Ku
  • Giovanni De Micheli

Table of contents

  1. Front Matter
    Pages i-xiii
  2. David C. Ku, Giovanni De Micheli
    Pages 1-17
  3. David C. Ku, Giovanni De Micheli
    Pages 19-46
  4. David C. Ku, Giovanni De Micheli
    Pages 47-60
  5. David C. Ku, Giovanni De Micheli
    Pages 61-81
  6. David C. Ku, Giovanni De Micheli
    Pages 83-111
  7. David C. Ku, Giovanni De Micheli
    Pages 113-162
  8. David C. Ku, Giovanni De Micheli
    Pages 163-181
  9. David C. Ku, Giovanni De Micheli
    Pages 183-212
  10. David C. Ku, Giovanni De Micheli
    Pages 213-236
  11. David C. Ku, Giovanni De Micheli
    Pages 237-252
  12. David C. Ku, Giovanni De Micheli
    Pages 253-274
  13. David C. Ku, Giovanni De Micheli
    Pages 275-280
  14. Back Matter
    Pages 281-294

About this book

Introduction

Computer-aided synthesis of digital circuits from behavioral level specifications offers an effective means to deal with increasing complexity of digital hardware design. High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses both theoretical and practical aspects in the design of a high-level synthesis system that transforms a behavioral level description of hardware to a synchronous logic-level implementation consisting of logic gates and registers.
High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses specific issues in applying high-level synthesis techniques to the design of ASICs. This complements previous results achieved in synthesis of general-purpose and signal processors, where data-path design is of utmost importance. In contrast, ASIC designs are often characterized by complex control schemes, to support communication and synchronization with the environment. The combined design of efficient data-path control-unit is the major contribution of this book.
Three requirements are important in modeling ASIC designs: concurrency, external synchronization, and detailed timing constraints. The objective of the research work presented here is to develop a hardware model incorporating these requirements as well as synthesis algorithms that operate on this hardware model.
The contributions of this book address both the theory and the implementation of algorithm for hardware synthesis.

Keywords

ASIC Hardware Signal algorithms communication complexity computer integrated circuit logic model modeling optimization

Authors and affiliations

  • David C. Ku
    • 1
  • Giovanni De Micheli
    • 2
  1. 1.Redwood Design AutomationStanford UniversityUSA
  2. 2.Stanford UniversityUSA

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4757-2117-1
  • Copyright Information Springer-Verlag US 1992
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4419-5129-8
  • Online ISBN 978-1-4757-2117-1
  • Series Print ISSN 0893-3405
  • Buy this book on publisher's site