Modeling Microprocessor Performance

  • Authors
  • Bibiche¬†Geuskens
  • Kenneth¬†Rose

Table of contents

  1. Front Matter
    Pages i-xvii
  2. Bibiche Geuskens, Kenneth Rose
    Pages 1-16
  3. Bibiche Geuskens, Kenneth Rose
    Pages 17-25
  4. Bibiche Geuskens, Kenneth Rose
    Pages 27-51
  5. Bibiche Geuskens, Kenneth Rose
    Pages 53-90
  6. Bibiche Geuskens, Kenneth Rose
    Pages 91-124
  7. Bibiche Geuskens, Kenneth Rose
    Pages 125-133
  8. Bibiche Geuskens, Kenneth Rose
    Pages 135-153
  9. Bibiche Geuskens, Kenneth Rose
    Pages 155-174
  10. Bibiche Geuskens, Kenneth Rose
    Pages 175-192
  11. Back Matter
    Pages 193-195

About this book

Introduction

Modeling Microprocessor Performance focuses on the development of a design and evaluation tool, named RIPE (Rensselaer Interconnect Performance Estimator). This tool analyzes the impact on wireability, clock frequency, power dissipation, and the reliability of single chip CMOS microprocessors as a function of interconnect, device, circuit, design and architectural parameters. It can accurately predict the overall performance of existing microprocessor systems. For the three major microprocessor architectures, DEC, PowerPC and Intel, the results have shown agreement within 10% on key parameters.
The models cover a broad range of issues that relate to the implementation and performance of single chip CMOS microprocessors. The book contains a detailed discussion of the various models and the underlying assumptions based on actual design practices. As such, RIPE and its models provide an insightful tool into single chip microprocessor design and its performance aspects. At the same time, it provides design and process engineers with the capability to model, evaluate, compare and optimize single chip microprocessor systems using advanced technology and design techniques at an early design stage without costly and time consuming implementation.
RIPE and its models demonstrate the factors which must be considered when estimating tradeoffs in device and interconnect technology and architecture design on microprocessor performance.

Keywords

CMOS development interconnect microprocessor model modeling processor reliability system transistor

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4615-5561-2
  • Copyright Information Springer Science+Business Media New York 1998
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4613-7543-2
  • Online ISBN 978-1-4615-5561-2
  • About this book