High-Level VLSI Synthesis

  • Raul Camposano
  • Wayne Wolf

Table of contents

  1. Front Matter
    Pages i-x
  2. Dirk Lanneer, Stefaan Note, Francis Depuydt, Marc Pauwels, Francky Catthoor, Gert Goossens et al.
    Pages 27-54
  3. Albert E. Casavant, Ki Soo Hwang, Kristen N. McNall
    Pages 55-78
  4. R. Camposano, R. A. Bergamaschi, C. E. Haynes, M. Payer, S. M. Wu
    Pages 79-104
  5. William P. Birmingham, Anurag P. Gupta, Daniel P. Siewiorek
    Pages 105-125
  6. Gaetano Borriello
    Pages 153-176
  7. David C. Ku, Giovanni De Micheli
    Pages 177-203
  8. Yukihiro Nakamura, Kiyoshi Oguri, Akira Nagoya
    Pages 205-229
  9. Wayne Wolf, Andrés Takach, Tien-Chien Lee
    Pages 231-254
  10. Yu-Chin Hsu, Youn-Long Lin
    Pages 283-306
  11. D. E. Thomas, T. E. Fuhrman
    Pages 307-329
  12. Alice C. Parker, Kayhan Küçükçakar, Shiv Prakash, Jen-Pin Weng
    Pages 331-354
  13. Wolfgang Rosenstiel, Heinrich Krämer
    Pages 355-382
  14. Back Matter
    Pages 383-390

About this book

Introduction

The time has come for high-level synthesis. When research into synthesizing hardware from abstract, program-like de­ scriptions started in the early 1970' s, there was no automated path from the register­ transfer design produced by high-level synthesis to a complete hardware imple­ mentation. As a result, it was very difficult to measure the effectiveness of high­ level synthesis methods; it was also hard to justify to users the need to automate architecture design when low-level design had to be completed manually. Today's more mature CAD techniques help close the gap between an automat­ ically synthesized design and a manufacturable design. Market pressures encour­ age designers to make use of any and all automated tools. Layout synthesis, logic synthesis, and specialized datapath generators make it feasible to quickly imple­ ment a register-transfer design in silicon,leaving designers more time to consider architectural improvements. As IC design becomes more automated, customers are increasing their demands; today's leading edge designers using logic synthesis systems are training themselves to be tomorrow's consumers of high-level synthe­ sis systems. The need for very fast turnaround, a competitive fabrication market WhlCh makes small-quantity ASIC manufacturing possible, and the ever growing co:n­ plexity of the systems being designed, all make higher-level design automaton inevitable.

Keywords

ASIC Hardware VLSI algorithms construction integrated circuit logic optimization

Editors and affiliations

  • Raul Camposano
    • 1
  • Wayne Wolf
    • 2
  1. 1.IBMUSA
  2. 2.Princeton UniversityUSA

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4615-3966-7
  • Copyright Information Kluwer Academic Publishers 1991
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4613-6771-0
  • Online ISBN 978-1-4615-3966-7
  • Series Print ISSN 0893-3405
  • About this book