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Matrix Computations on Systolic-Type Arrays

  • Jaime H. Moreno
  • Tomás Lang

Part of the The Kluwer International Series in Engineering and Computer Science book series (SECS, volume 174)

Table of contents

  1. Front Matter
    Pages i-xxv
  2. Jaime H. Moreno, Tomás Lang
    Pages 1-13
  3. Jaime H. Moreno, Tomás Lang
    Pages 15-43
  4. Jaime H. Moreno, Tomás Lang
    Pages 45-90
  5. Jaime H. Moreno, Tomás Lang
    Pages 91-134
  6. Jaime H. Moreno, Tomás Lang
    Pages 135-170
  7. Jaime H. Moreno, Tomás Lang
    Pages 171-198
  8. Jaime H. Moreno, Tomás Lang
    Pages 199-223
  9. Jaime H. Moreno, Tomás Lang
    Pages 225-257
  10. Jaime H. Moreno, Tomás Lang
    Pages 259-265
  11. Back Matter
    Pages 267-280

About this book

Introduction

Matrix Computations on Systolic-Type Arrays provides a framework which permits a good understanding of the features and limitations of processor arrays for matrix algorithms. It describes the tradeoffs among the characteristics of these systems, such as internal storage and communication bandwidth, and the impact on overall performance and cost. A system which allows for the analysis of methods for the design/mapping of matrix algorithms is also presented. This method identifies stages in the design/mapping process and the capabilities required at each stage.
Matrix Computations on Systolic-Type Arrays provides a much needed description of the area of processor arrays for matrix algorithms and of the methods used to derive those arrays. The ideas developed here reduce the space of solutions in the design/mapping process by establishing clear criteria to select among possible options as well as by a-priori rejection of alternatives which are not adequate (but which are considered in other approaches). The end result is a method which is more specific than other techniques previously available (suitable for a class of matrix algorithms) but which is more systematic, better defined and more effective in reaching the desired objectives.
Matrix Computations on Systolic-Type Arrays will interest researchers and professionals who are looking for systematic mechanisms to implement matrix algorithms either as algorithm-specific structures or using specialized architectures. It provides tools that simplify the design/mapping process without introducing degradation, and that permit tradeoffs between performance/cost measures selected by the designer.

Keywords

algorithm algorithms communication processor tables

Authors and affiliations

  • Jaime H. Moreno
    • 1
  • Tomás Lang
    • 2
  1. 1.Departamento de Ingeniería EléctricaUniversidad de ConcepciónChile
  2. 2.Departament d’Arquitectura de ComputadorsUniversitat Politècnica de CatalunyaBarcelonaSpain

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4615-3610-9
  • Copyright Information Kluwer Academic Publishers 1992
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4613-6604-1
  • Online ISBN 978-1-4615-3610-9
  • Series Print ISSN 0893-3405
  • Buy this book on publisher's site