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VHDL for Simulation, Synthesis and Formal Proofs of Hardware

  • Jean Mermet

Part of the The Kluwer International Series in Engineering and Computer Science book series (SECS, volume 183)

Table of contents

  1. Front Matter
    Pages i-ix
  2. Introduction

  3. Simulation

    1. Front Matter
      Pages 15-15
    2. Fuhong Liu, Adam Pawlak
      Pages 17-32
    3. M. Dufresne, K. Khordoc, E. Cerny
      Pages 33-42
    4. K. Khordoc, M. Biotteau, E. Cerny
      Pages 43-62
    5. Matti Sipola, Juha-Pekka Soininen, Jorma Kivelä
      Pages 73-86
    6. Peter Connor, Sanjay Nayak, Joyce Kraley, Victor Berman
      Pages 87-98
  4. Synthesis

    1. Front Matter
      Pages 99-99
    2. Haluk Konuk, F. Erich Marschner
      Pages 101-115
    3. Robert A. Cottrell
      Pages 135-147
    4. John Elliott, Paul Harper
      Pages 163-175
  5. Formal Verifications and Semantics

    1. Front Matter
      Pages 177-177
    2. Alain Debreil, Christian Berthet, Ahmed Jerraya
      Pages 179-193
    3. Ashraf Salem, Dominique Borrione
      Pages 195-206
    4. R. A. J. Marshall, H. J. Kahn
      Pages 207-225
    5. Dominique Borrione, Laurence Pierre, Ashraf Salem
      Pages 227-243
    6. Philip A. Wilsey
      Pages 245-256
  6. System Level Design and Modelling

    1. Front Matter
      Pages 257-257
    2. Franz J. Rammig
      Pages 259-276
    3. Claude Le Faou, Jean Mermet
      Pages 291-307

About this book

Introduction

The success of VHDL since it has been balloted in 1987 as an IEEE standard may look incomprehensible to the large population of hardware designers, who had never heared of Hardware Description Languages before (for at least 90% of them), as well as to the few hundreds of specialists who had been working on these languages for a long time (25 years for some of them). Until 1988, only a very small subset of designers, in a few large companies, were used to describe their designs using a proprietary HDL, or sometimes a HDL inherited from a University when some software environment happened to be developped around it, allowing usability by third parties. A number of benefits were definitely recognized to this practice, such as functional verification of a specification through simulation, first performance evaluation of a tentative design, and sometimes automatic microprogram generation or even automatic high level synthesis. As there was apparently no market for HDL's, the ECAD vendors did not care about them, start-up companies were seldom able to survive in this area, and large users of proprietary tools were spending more and more people and money just to maintain their internal system.

Keywords

ASIC C programming language Constraint VHDL circuit design computer-aided design (CAD) formal verification model modeling simulation verification

Editors and affiliations

  • Jean Mermet
    • 1
  1. 1.Institut Méditerranéen de TechnologieGermany

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4615-3562-1
  • Copyright Information Kluwer Academic Publishers 1992
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4613-6582-2
  • Online ISBN 978-1-4615-3562-1
  • Series Print ISSN 0893-3405
  • Buy this book on publisher's site