Fast Simulation of Computer Architectures

  • Thomas M. Conte
  • Charles E. Gimarc

Table of contents

  1. Front Matter
    Pages i-ix
  2. Thomas M. Conte, Charles E. Gimarc
    Pages 1-4
  3. Jim Pierce, Michael D. Smith, Trevor Mudge
    Pages 47-86
  4. Thomas M. Conte
    Pages 87-107
  5. Rabin A. Sugumar, Santosh G. Abraham
    Pages 109-144
  6. Kishore N. Menezes
    Pages 171-203
  7. Back Matter
    Pages 239-244

About this book


Chapters in Fast Simulation of Computer Architectures cover topics such as how to collect traces, emulate instruction sets, simulate microprocessors using execution-driven techniques, evaluate memory hierarchies, apply statistical sampling to simulation, and how to augment simulation with performance bound models. The chapters have been written by many of the leading researchers in the area, in a collaboration that ensures that the material is both coherent and cohesive.
Audience: Of tremendous interest to practising computer architect designers seeking timely solutions to tough evaluation problems, and to advanced upper division undergraduate and graduate students of the field. Useful study aids are provided by the problems at the end of Chapters 2 through 8.


architecture computer computer architecture processor

Editors and affiliations

  • Thomas M. Conte
    • 1
  • Charles E. Gimarc
    • 2
  1. 1.University of South CarolinaColumbiaUSA
  2. 2.AT & T Global Information SolutionsWest ColumbiaUSA

Bibliographic information

  • DOI
  • Copyright Information Springer Science+Business Media New York 1995
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4613-6002-5
  • Online ISBN 978-1-4615-2361-1
  • Buy this book on publisher's site