VHDL Modeling for Digital Design Synthesis

  • Yu-Chin Hsu
  • Kevin F. Tsai
  • Jessie T. Liu
  • Eric S. Lin

Table of contents

  1. Front Matter
    Pages i-xix
  2. Yu-Chin Hsu, Kevin F. Tsai, Jessie T. Liu, Eric S. Lin
    Pages 1-14
  3. Yu-Chin Hsu, Kevin F. Tsai, Jessie T. Liu, Eric S. Lin
    Pages 15-34
  4. Yu-Chin Hsu, Kevin F. Tsai, Jessie T. Liu, Eric S. Lin
    Pages 35-55
  5. Yu-Chin Hsu, Kevin F. Tsai, Jessie T. Liu, Eric S. Lin
    Pages 57-74
  6. Yu-Chin Hsu, Kevin F. Tsai, Jessie T. Liu, Eric S. Lin
    Pages 75-87
  7. Yu-Chin Hsu, Kevin F. Tsai, Jessie T. Liu, Eric S. Lin
    Pages 89-103
  8. Yu-Chin Hsu, Kevin F. Tsai, Jessie T. Liu, Eric S. Lin
    Pages 105-128
  9. Yu-Chin Hsu, Kevin F. Tsai, Jessie T. Liu, Eric S. Lin
    Pages 129-161
  10. Yu-Chin Hsu, Kevin F. Tsai, Jessie T. Liu, Eric S. Lin
    Pages 163-190
  11. Yu-Chin Hsu, Kevin F. Tsai, Jessie T. Liu, Eric S. Lin
    Pages 191-225
  12. Yu-Chin Hsu, Kevin F. Tsai, Jessie T. Liu, Eric S. Lin
    Pages 227-242
  13. Yu-Chin Hsu, Kevin F. Tsai, Jessie T. Liu, Eric S. Lin
    Pages 243-278
  14. Yu-Chin Hsu, Kevin F. Tsai, Jessie T. Liu, Eric S. Lin
    Pages 279-294
  15. Yu-Chin Hsu, Kevin F. Tsai, Jessie T. Liu, Eric S. Lin
    Pages 295-321
  16. Back Matter
    Pages 323-356

About this book

Introduction

The purpose of this book is to introduce VHSIC Hardware Description Lan­ guage (VHDL) and its use for synthesis. VHDL is a hardware description language which provides a means of specifying a digital system over different levels of abstraction. It supports behavior specification during the early stages of a design process and structural specification during the later implementation stages. VHDL was originally introduced as a hardware description language that per­ mitted the simulation of digital designs. It is now increasingly used for design specifications that are given as the input to synthesis tools which translate the specifications into netlists from which the physical systems can be built. One problem with this use of VHDL is that not all of its constructs are useful in synthesis. The specification of delay in signal assignments does not have a clear meaning in synthesis, where delays have already been determined by the im­ plementationtechnolo~y. VHDL has data-structures such as files and pointers, useful for simulation purposes but not for actual synthesis. As a result synthe­ sis tools accept only subsets of VHDL. This book tries to cover the synthesis aspect of VHDL, while keeping the simulation-specifics to a minimum. This book is suitable for working professionals as well as for graduate or under­ graduate study. Readers can view this book as a way to get acquainted with VHDL and how it can be used in modeling of digital designs.

Keywords

Hardware Standard VHDL algorithms design process digital design modeling simulation

Authors and affiliations

  • Yu-Chin Hsu
    • 1
  • Kevin F. Tsai
    • 1
  • Jessie T. Liu
    • 1
  • Eric S. Lin
    • 1
  1. 1.University of CaliforniaRiverside

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4615-2343-7
  • Copyright Information Springer Science+Business Media New York 1995
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4613-5993-7
  • Online ISBN 978-1-4615-2343-7
  • About this book