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Digit-Serial Computation

  • Richard Hartley
  • Keshab K. Parhi

Table of contents

  1. Front Matter
    Pages i-xiii
  2. Richard Hartley, Keshab K. Parhi
    Pages 1-26
  3. Richard Hartley, Keshab K. Parhi
    Pages 27-41
  4. Richard Hartley, Keshab K. Parhi
    Pages 43-61
  5. Richard Hartley, Keshab K. Parhi
    Pages 63-93
  6. Richard Hartley, Keshab K. Parhi
    Pages 95-106
  7. Richard Hartley, Keshab K. Parhi
    Pages 107-135
  8. Richard Hartley, Keshab K. Parhi
    Pages 137-146
  9. Richard Hartley, Keshab K. Parhi
    Pages 147-163
  10. Richard Hartley, Keshab K. Parhi
    Pages 165-182
  11. Richard Hartley, Keshab K. Parhi
    Pages 183-194
  12. Richard Hartley, Keshab K. Parhi
    Pages 195-215
  13. Richard Hartley, Keshab K. Parhi
    Pages 217-252
  14. Richard Hartley, Keshab K. Parhi
    Pages 253-290
  15. Back Matter
    Pages 291-306

About this book

Introduction

Digital signal processing (DSP) is used in a wide range of applications such as speech, telephone, mobile radio, video, radar and sonar. The sample rate requirements of these applications range from 10 KHz to 100 MHz. Real time implementation of these systems requires design of hardware which can process signal samples as these are received from the source, as opposed to storing them in buffers and processing them in batch mode. Efficient implementation of real­ time hardware for DSP applications requires study of families of architectures and implementation styles out of which an appropriate architecture can be selected for a specified application. To this end, the digit-serial implementation style is proposed as an appropriate design methodology for cases where bit-serial systems cannot meet the sample rate requirements, and bit-parallel systems require excessive hardware. The number of bits processed in a clock cycle is referred to as the digit-size. The hardware complexity and the achievable sample rate increase with increase in the digit-size. As special cases, a digit­ serial system is reduced to bit-serial or bit-parallel when the digit-size is selected to equal one or the word-length, respectively. A family of implementations can be obtained by changing the digit-size parameter, thus permitting an optimal trade-off between throughput and size. Because of their structured architecture, digit-serial designs lend themselves to automatic compilation from algorithmic descriptions. An implementation of this design methodology, the Parsifal silicon compiler was developed at the General Electric Corporate Research and Development laboratory.

Keywords

Hardware Signal algorithm circuit digital signal processing digital signal processor radar radio signal processing

Authors and affiliations

  • Richard Hartley
    • 1
  • Keshab K. Parhi
    • 2
  1. 1.General Electrical CRDUSA
  2. 2.University of MinnesotaUSA

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4615-2327-7
  • Copyright Information Kluwer Academic Publishers 1995
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4613-5985-2
  • Online ISBN 978-1-4615-2327-7
  • Series Print ISSN 0893-3405
  • Buy this book on publisher's site