Low Power Digital CMOS Design

  • Anantha P. Chandrakasan
  • Robert W. Brodersen

Table of contents

  1. Front Matter
    Pages i-xi
  2. Anantha P. Chandrakasan, Robert W. Brodersen
    Pages 1-10
  3. James D. Meindl
    Pages 11-53
  4. Anantha P. Chandrakasan, Robert W. Brodersen
    Pages 55-104
  5. Anantha P. Chandrakasan, Robert W. Brodersen
    Pages 105-140
  6. Anthony J. Stratakos, Charles R. Sullivan, Seth R. Sanders
    Pages 141-180
  7. Lars Svensson
    Pages 181-218
  8. Anantha P. Chandrakasan, Robert W. Brodersen
    Pages 219-258
  9. Anantha P. Chandrakasan, Robert W. Brodersen
    Pages 259-308
  10. Anantha P. Chandrakasan, Robert W. Brodersen
    Pages 309-366
  11. Mani B. Srivastava
    Pages 367-396
  12. Anantha P. Chandrakasan, Robert W. Brodersen
    Pages 397-400
  13. Back Matter
    Pages 401-409

About this book

Introduction

Power consumption has become a major design consideration for battery-operated, portable systems as well as high-performance, desktop systems. Strict limitations on power dissipation must be met by the designer while still meeting ever higher computational requirements. A comprehensive approach is thus required at all levels of system design, ranging from algorithms and architectures to the logic styles and the underlying technology.
Potentially one of the most important techniques involves combining architecture optimization with voltage scaling, allowing a trade-off between silicon area and low-power operation. Architectural optimization enables supply voltages of the order of 1 V using standard CMOS technology. Several techniques can also be used to minimize the switched capacitance, including representation, optimizing signal correlations, minimizing spurious transitions, optimizing sequencing of operations, activity-driven power down, etc. The high- efficiency of DC-DC converter circuitry required for efficient, low-voltage and low-current level operation is described by Stratakos, Sullivan and Sanders. The application of various low-power techniques to a chip set for multimedia applications shows that orders-of-magnitude reduction in power consumption is possible.
The book also features an analysis by Professor Meindl of the fundamental limits of power consumption achievable at all levels of the design hierarchy. Svensson, of ISI, describes emerging adiabatic switching techniques that can break the CV2f barrier and reduce the energy per computation at a fixed voltage. Srivastava, of AT&T, presents the application of aggressive shut-down techniques to microprocessor applications.

Keywords

CMOS Potential Signal Standard computer logic microprocessor multimedia

Authors and affiliations

  • Anantha P. Chandrakasan
    • 1
  • Robert W. Brodersen
    • 2
  1. 1.Massachusetts Institute of TechnologyUSA
  2. 2.University of California/BerkeleyUSA

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4615-2325-3
  • Copyright Information Kluwer Academic Publishers 1995
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4613-5984-5
  • Online ISBN 978-1-4615-2325-3
  • About this book