UTLEON3: Exploring Fine-Grain Multi-Threading in FPGAs

  • Martin Daněk
  • Leoš Kafka
  • Lukáš Kohout
  • Jaroslav Sýkora
  • Roman Bartosinski

Table of contents

  1. Front Matter
    Pages i-xviii
  2. Programming Interface

    1. Front Matter
      Pages 1-1
    2. Martin Daněk, Leoš Kafka, Lukáš Kohout, Jaroslav Sýkora, Roman Bartosiński
      Pages 3-7
    3. Martin Daněk, Leoš Kafka, Lukáš Kohout, Jaroslav Sýkora, Roman Bartosiński
      Pages 9-14
    4. Martin Daněk, Leoš Kafka, Lukáš Kohout, Jaroslav Sýkora, Roman Bartosiński
      Pages 15-43
    5. Martin Daněk, Leoš Kafka, Lukáš Kohout, Jaroslav Sýkora, Roman Bartosiński
      Pages 45-66
    6. Martin Daněk, Leoš Kafka, Lukáš Kohout, Jaroslav Sýkora, Roman Bartosiński
      Pages 67-77
  3. Implementation

    1. Front Matter
      Pages 79-79
    2. Martin Daněk, Leoš Kafka, Lukáš Kohout, Jaroslav Sýkora, Roman Bartosiński
      Pages 81-109
    3. Martin Daněk, Leoš Kafka, Lukáš Kohout, Jaroslav Sýkora, Roman Bartosiński
      Pages 111-126
    4. Martin Daněk, Leoš Kafka, Lukáš Kohout, Jaroslav Sýkora, Roman Bartosiński
      Pages 127-158
    5. Martin Daněk, Leoš Kafka, Lukáš Kohout, Jaroslav Sýkora, Roman Bartosiński
      Pages 159-172
  4. Back Matter
    Pages 173-219

About this book

Introduction

This book describes a specification, microarchitecture, VHDL implementation and evaluation of a SPARC v8 CPU with fine-grain multi-threading, called micro-threading. The CPU, named UTLEON3, is an alternative platform for exploring CPU multi-threading that is compatible with the industry-standard GRLIB package. The processor microarchitecture was designed to map in an efficient way the data-flow scheme on a classical von Neumann pipelined processing used in common processors, while retaining full binary compatibility with existing legacy programs. 

  • Describes and documents a working SPARC v8, with fine-grain multithreading and fast context switch;
  • Provides VHDL sources for the described processor;
  • Describes a latency-tolerant framework for coupling hardware accelerators to microthreaded processor pipelines;
  • Includes programming by example in the micro-threaded assembly language.

 

 

Keywords

FPGA Fine-Grained Computing GRLIB Micro-Threading Multi-Threaded Computing RISC SPARC SPARC v8

Authors and affiliations

  • Martin Daněk
    • 1
  • Leoš Kafka
    • 2
  • Lukáš Kohout
    • 3
  • Jaroslav Sýkora
    • 4
  • Roman Bartosinski
    • 5
  1. 1., Pod Vodárenskou věží 1143/4ÚTIA AV ČR, v.v.i.Praha 8Czech Republic
  2. 2., Pod Vodárenskou věží 1143/4ÚTIA AV ČR, v.v.i.Praha 8Czech Republic
  3. 3., Pod Vodárenskou věží 1143/4ÚTIA AV ČR, v.v.i.Praha 8Czech Republic
  4. 4., Pod Vodárenskou věží 1143/4ÚTIA AV ČR, v.v.i.Praha 8Czech Republic
  5. 5., Pod Vodárenskou věží 1143/4ÚTIA AV ČR, v.v.i.Praha 8Czech Republic

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4614-2410-9
  • Copyright Information Springer Science+Business Media, LLC 2013
  • Publisher Name Springer, New York, NY
  • eBook Packages Engineering
  • Print ISBN 978-1-4614-2409-3
  • Online ISBN 978-1-4614-2410-9
  • About this book