Low Power Design with High-Level Power Estimation and Power-Aware Synthesis

  • Sumit Ahuja
  • Avinash Lakshminarayana
  • Sandeep Kumar Shukla

Table of contents

  1. Front Matter
    Pages i-xxii
  2. Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla
    Pages 1-12
  3. Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla
    Pages 13-29
  4. Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla
    Pages 31-43
  5. Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla
    Pages 45-57
  6. Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla
    Pages 59-70
  7. Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla
    Pages 71-80
  8. Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla
    Pages 81-92
  9. Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla
    Pages 93-103
  10. Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla
    Pages 105-118
  11. Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla
    Pages 119-129
  12. Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla
    Pages 131-141
  13. Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla
    Pages 143-156
  14. Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla
    Pages 157-161
  15. Back Matter
    Pages 163-170

About this book

Introduction

Low-power ASIC/FPGA based designs are important due to the need for extended battery life, reduced form factor, and lower packaging and cooling costs for electronic devices. These products require fast turnaround time because of the increasing demand for handheld electronic devices such as cell-phones, PDAs and high performance machines for data centers. To achieve short time to market, design flows must facilitate a much shortened time-to-product requirement. High-level modeling, architectural exploration and direct synthesis of design from high level description enable this design process.

This book presents novel research techniques, algorithms,methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.

  • Integrates power estimation and reduction for high level synthesis, with low-power, high-level design;
  • Shows specific techniques for ASICs as well as FPGA based SoC designs, allowing readers to evaluate and explore various possible alternatives;
  • Covers techniques from RTL/gate-level to hardware software co-design.

Keywords

Hardware Software Co-Design High Level Synthesis Low Power Design Power Aware Synthesis System Level Design

Authors and affiliations

  • Sumit Ahuja
    • 1
  • Avinash Lakshminarayana
    • 2
  • Sandeep Kumar Shukla
    • 3
  1. 1., ECE DepartmentVirginia Polytechnic Institute and StateBlacksburgUSA
  2. 2., ECE DepartmentVirginia TechBlacksburgUSA
  3. 3.Bradley Dept. Electrical &, Computer EngineeringVirginia TechBlacksburgUSA

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4614-0872-7
  • Copyright Information Springer Science+Business Media, LLC 2012
  • Publisher Name Springer, New York, NY
  • eBook Packages Engineering
  • Print ISBN 978-1-4614-0871-0
  • Online ISBN 978-1-4614-0872-7
  • About this book