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Logic Minimization Algorithms for VLSI Synthesis

  • Authors
  • Robert K. Brayton
  • Gary D. Hachtel
  • Curtis T. McMullen
  • Alberto L. Sangiovanni-Vincentelli

Table of contents

  1. Front Matter
    Pages i-xi
  2. Robert K. Brayton, Gary D. Hachtel, Curtis T. McMullen, Alberto L. Sangiovanni-Vincentelli
    Pages 1-14
  3. Robert K. Brayton, Gary D. Hachtel, Curtis T. McMullen, Alberto L. Sangiovanni-Vincentelli
    Pages 15-28
  4. Robert K. Brayton, Gary D. Hachtel, Curtis T. McMullen, Alberto L. Sangiovanni-Vincentelli
    Pages 29-53
  5. Robert K. Brayton, Gary D. Hachtel, Curtis T. McMullen, Alberto L. Sangiovanni-Vincentelli
    Pages 54-138
  6. Robert K. Brayton, Gary D. Hachtel, Curtis T. McMullen, Alberto L. Sangiovanni-Vincentelli
    Pages 139-147
  7. Robert K. Brayton, Gary D. Hachtel, Curtis T. McMullen, Alberto L. Sangiovanni-Vincentelli
    Pages 148-159
  8. Robert K. Brayton, Gary D. Hachtel, Curtis T. McMullen, Alberto L. Sangiovanni-Vincentelli
    Pages 160-173
  9. Back Matter
    Pages 174-193

About this book

Introduction

The roots of the project which culminates with the writing of this book can be traced to the work on logic synthesis started in 1979 at the IBM Watson Research Center and at University of California, Berkeley. During the preliminary phases of these projects, the impor­ tance of logic minimization for the synthesis of area and performance effective circuits clearly emerged. In 1980, Richard Newton stirred our interest by pointing out new heuristic algorithms for two-level logic minimization and the potential for improving upon existing approaches. In the summer of 1981, the authors organized and participated in a seminar on logic manipulation at IBM Research. One of the goals of the seminar was to study the literature on logic minimization and to look at heuristic algorithms from a fundamental and comparative point of view. The fruits of this investigation were surprisingly abundant: it was apparent from an initial implementation of recursive logic minimiza­ tion (ESPRESSO-I) that, if we merged our new results into a two-level minimization program, an important step forward in automatic logic synthesis could result. ESPRESSO-II was born and an APL implemen­ tation was created in the summer of 1982. The results of preliminary tests on a fairly large set of industrial examples were good enough to justify the publication of our algorithms. It is hoped that the strength and speed of our minimizer warrant its Italian name, which denotes both express delivery and a specially-brewed black coffee.

Keywords

Maxima Phase Potential VLSI algebra algorithms calculus design history integrated circuit logic organization

Bibliographic information

  • DOI https://doi.org/10.1007/978-1-4613-2821-6
  • Copyright Information Springer-Verlag US 1984
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4612-9784-0
  • Online ISBN 978-1-4613-2821-6
  • Series Print ISSN 0893-3405
  • Buy this book on publisher's site